This work proposes a low offset asymmetric sense amplifier (LO-ASA) to perform in-memory boolean logic computations. The design uses a single capacitor to reduce the offset introduced by the input transistors of the sense amplifier. The resultant low offset sense amplifier becomes asymmetric and helps to implement multiple logic gates like$NOR$,$OR$,$AND$,$NAND$,$XNOR$and$XOR$. The proposed$128\times 128$SRAM architecture requires only one LO-ASA per column to implement the desired logic gates using a logic selection circuit. The circuit is designed and simulated in UMC 65 nm CMOS technology using a 1.2 V power supply. The worst case standard deviation of offset observed for the conventional current latch sense amplifier and the proposed LO-ASA are 12.2 mV and 9.1 mV, respectively, evaluated for 1000 Monte Carlo runs at$3\sigma $deviation. The proposed sense amplifier results in a yield of 99.7%, 100%, and 99.6%, respectively corresponding to boolean logic$NOR/OR$,$AND/NAND$, and$XNOR/XOR$at a nominal temperature of 27°C. In addition, the worst-case power delay product of 5.2 fJ, 9.5 fJ, and 26 fJ is achieved for$NOR$,$AND$, and$XNOR$gates, respectively.

This paper addresses the challenges of efficient image acquisition and processing in resource-constrained environments by introducing sparsity-driven CMOS Image Sensor (CIS) architecture coupled with Vision Transformers (ViTs). Our proposed approach incorporates a sensor-level dimensionality reduction technique to capture sparse and high-relevance features for enhancing power and computational efficiency at the sensor level. Key proposals for the pipeline include a re-designed CIS architecture that enables selective feature acquisition through on-sensor edge detection, an adaptive threshold mechanism for reducing ADC operations (> 50% for τ = 0.9) through edge-based pixel selection, and a co-designed memory management strategy focused on patch-wise data retention. Experimental evaluations on CIFAR-10, STL-10, Food-101, and Caltech-256 show a reduction of ≈ 89%, 78%, 76%, and 81% data volume for 100 selected patches while maintaining accuracies of ≈ 94%, 93%, 74%, and 82%, respectively. These improvements in the acquisition architecture demonstrate scalable, real-time processing potential on edge devices, making the proposed architecture a robust solution for low-power applications requiring efficient data acquisition and processing, particularly for ViTs.

An always-on intelligent system comprising of an image sensor requires continuous functioning of each pixel. This includes sensing the illumination content of the scene and also the conversion of the analog values into their digital representations. Therefore, power consumption during analog to digital conversion and computational cost at the image sensor module become critical while designing a system that is always-on and incorporates intelligence near the sensor module. This work focuses on the inherent property of the ADC for converting the analog pixel values to digital values by taking a defined number of analog-to-digital converter (ADC) cycles. The design factors considered are 1) Power saving due to reduced ADC conversion cycles for each pixel; 2) The reduced bit-precision of the processing unit to reduce hardware cost; 3) The dataflow design throughhls4ml, which produces parallel computational modes for low latency CNN architectures. The proposed work implements two lightweight CNN models with reduced parameters as compared to the original architectural models of VGG16 (like) and SqueezeNet (like) which are trained in Qkeras and deployed on Zynq UltraScale+ MPSoC board. In addition, the design pipeline is validated on the MobileNetV2 and GhostNet architectures to demonstrate its generalization ability. A detailed analysis shows that limiting the number of ADC bits from 8 to 4 reduces the mean accuracy merely from 50.3 to 49.17 for VGG16 (like) and 67.83 to 67.80 for SqueezeNet (like) model, however, the readout power is significantly reduced from 140.45 mW to 7.7 mW for STL-10 dataset with$96\times96$image resolution. Additional experiments are conducted with CIFAR-10 and mini-ImageNet datasets for classification and with Oxford-IIIT Pet Dataset for segmentation. The proposed work, thus, provides empirical evidence that a reasonable performance for intelligent vision tasks with power saving can be achieved by tuning CNN models to work with reduced ADC bit precision.

This work proposes a single capacitor-based offset reduction technique for dynamic comparators. It additionally uses only one capacitor and two transistors to reduce the offset introduced due to threshold mismatch, resulting in an energy-efficient design. The proposed technique reduces the offset by four to six times compared to the conventional design for the entire input range. The comparator is designed in 65 nm CMOS process using 1.2 V power supply. It occupies an area of$21.2\ \mu\mathrm{m}\times 16\ \mu\mathrm{m}$. The performance of comparator is verified using post-layout simulations. The maximum operating frequency of comparator is 2 GHz and it consumes 51 fJ of energy per conversion cycle. The Monte-Carlo simulations performed for 500 samples result in worst-case offset of 1.7 mV.

An input folding cyclic ADC for column-parallel readout in CMOS image sensor is proposed. A double sampling circuit in the CMOS image sensor is reused to perform input folding operation in cyclic ADC. In addition, a push-pull configuration based slew rate enhancement technique is used to reduce the settling time of multiplying digital to analog converter. The ADC results in a conversion rate of 1.38 MS/s while consuming 560 $\mu$W of power. A prototype CMOS image sensor, with 12-bit column-parallel cyclic ADC, is designed and fabricated in AMS 350 nm CMOS OPTO process at 3.3 V power supply. For a $96\times 64$ pixel array, the row readout time of 720 ns is achieved, which is two to five times smaller compared to the state-of-the-art.

A capacitive mismatch insensitive (CMI) multiplying digital to analog converter (MDAC) is proposed in this paper. MDAC requires only four clock phases for 2-bit conversion along with minimal use of circuit components. The reduction in number of clock cycles and improvement in speed is observed at the architecture level as well as circuit level compared to most of the circuits reported in literature. The CMI MDAC is designed and fabricated in AMS 350 nm CMOS process using 3.3 V power supply. The MDAC occupies an area of $70 \mu \mathrm{m}\times 150 \mu \mathrm{m}$. It requires only 240 ns to obtain the residue voltage and consumes $169.5 \mu \mathrm{W}$ of power. The proposed MDAC will result in an area efficient and high resolution readout when used in column-parallel cyclic ADC in CMOS image sensors.

A high speed, low energy dynamic comparator using current recycling approach is proposed in this paper. The current flowing through the preamplifier during the regenerative phase is sensed and added to the regenerative nodes for high speed operation. The increment in power is further compensated using additional clock signal to prevent the full discharge of output nodes of the preamplifier. The comparator is designed and simulated in UMC 180 nm CMOS process at 1.8 V power supply. The performance of comparator is verified at different process corners. The designed comparator operates at a frequency of 500 MHz and consumes 162 fJ of energy. The variations in latency is observed from 10 ps to 1 ns for working range of 1 V. The Monte Carlo simulations are performed for 200 samples resulting in a mean offset of-0.0056 mV and standard deviation of 7.42 mV.

A compressive acquisition technique for on-array image compression is proposed in this paper. It capitalizes on representation ability of accumulated spatial gradients of the acquired scene. The local variations inferred from strength of the accumulated gradients are used as cues to vary number of samples read through the image sensor readout. Such sampling enables the reconstruction using traditional interpolation techniques with desired quality. The proposed method is first verified using MATLAB simulations, where on an average, a compression of 87% is achieved, for a threshold of 40 intensity levels. The images are reconstructed using nearest neighbour interpolation (NNI) method which results in a mean peak signal to noise ratio (PSNR) value of 29.09 dB. The reconstructed images are further enhanced using deep convolutional neural network, which improves the PSNR to 32.46 dB. The biggest advantage of the proposed technique is low-complex hardware design. As a proof of concept, a hardware implementation of the technique is performed using discrete components. Pixel intensity values of standard images are converted into analog voltages using a data acquisition system and mapped in the input voltage range of 1.5 V -5.5 V. For a threshold of 3.8 V, the compression of 81% - 83% is observed for the considered images. The proposed technique is simple and effective, and is suitable for low-power complementary metal oxide semiconductor (CMOS) image sensors.

A 12-bit, programmable hybrid ADC for CMOS image sensor is proposed in this paper. The hybrid ADC internally uses cyclic-SAR architecture and results in an area efficient and high speed design. To minimize the total column ADC area, the elements of cyclic ADC are reused for SAR operation. The 12-bit programmable ADC can be operated either in high resolution mode or high speed mode depending on the number of bits allocated per stage. The prototype CMOS image sensor is designed and fabricated in AMS 350 nm CMOS OPTO process. A three-transistor pixel architecture followed by column parallel-readout circuit is implemented in a 9 μm column pitch. A prototype 128 × 96 image sensor consumes 62.7 mW of power at 3.3 V power supply.

A 12-bit, 1.67-MS/s, two-stage cyclic ADC, using a 1.5-bit algorithm in a 2.5-bit framework is proposed in this brief. The number of accurate comparators is reduced to half as compared with the conventional 2.5-bit stage, which reduces the power consumption. Furthermore, the pipelined operation of the two stages reduces the total number of clock-cycles, which improves the conversion rate. The proposed ADC is designed and fabricated in a standard 180-nm CMOS technology. The obtained differential nonlinearity and integral nonlinearity are +0.5/-0.5 LSB and +0.8/-0.9 LSB, respectively. The ADC consumes 435-μW of power and occupies an area of 0.045 mm2. The postlayout simulations of ADC designed in a column-pitch of 5.6 μm show that it is suitable for column-parallel readout in CMOS image sensors.

A 12-bit, 1 MS/s, two-stage cyclic ADC, with novel 2.5-bit/cycle architecture is proposed in this paper. A 1.5-bit algorithm is used in a 2.5-bit framework, which reduces the required number of accurate comparators and power consumption by 42%. Further, the ADC shows 46% improvement in the conversion rate as compared to the state-of-the-art two-stage cyclic ADC. The proposed ADC is designed and fabricated in a standard 180 nm CMOS technology. The obtained values of DNL and INL are +0.5/-0.5 LSB and +0.8/-0.9 LSB respectively. The ADC consumes 0.8 mW of power and occupies an area of 0.045 mm2with a FoM of 0.19 pJ/conversion-step. The proposed ADC when designed in a column pitch of 5.6 μm, will result in a frame-rate of 1000 frames/sec for a 1 Mpixel array.

A low latency and a low power comparator is presented in this paper. The concept of current aiding at the output nodes of SR latch is proposed to enhance the switching speed of the comparator. The current flowing through the output nodes of regenerative latch is sensed and the amplified difference of these two currents is applied to the output nodes of SR latch. The circuit is designed and simulated in UMC 180 nm CMOS technology. Circuit consumes total power of 4.289 μW while operating at the clock frequency of 20 MHz. Measurement results proved that the designed comparator requires maximum of three clock cycles to perform switching for the input range 250-850 mV.