A hierarchical diagnosis algorithm is presented for testing identical units in a system. As all units are similar, it is essential that the test process be parallelized to enable test of multiple units for the cost of testing one unit. With this objective in mind, we propose a novel test architecture consisting of a hierarchy of testers in a system to test all the units simultaneously. In this approach, special test chips are placed at strategic locations in a system to compute a "golden response" by analyzing the responses of all units. The responses are propagated up the hierarchy of testers. At each level, the testers analyze the data and pass golden response computation data to testers at higher level. The tester at the top of the hierarchy computes the golden response and the test result is percolated down to the testers at the lowest level that identify faulty and fault-free units. Using this diagnosis approach, almost all units are correctly diagnosed, even when yields are as low as 40 percent. The hardware architecture of all test chips is identical and simple. This approach can be used for testing massively parallel multiprocessor systems, MCMs fabricated on a large area panel, and integrated circuits on silicon wafers.

A boundary scan-based algorithm is presented for testing iterative arrays of identical units such as integrated circuits on silicon wafers, MCMs fabricated on a large area panel, and multiprocessor systems. As all the units are similar, it is critical that the test process be parallelized in order that multiple units may be tested for the cost of testing one unit. With this objective in mind, we propose a parallel and pipelined boundary scan standard-based scheme for testing all units simultaneously. In this scheme, the test vectors and the corresponding correct-response vectors are both scanned into the scan chain of the units in an interleaved fashion, optimally utilizing the resources of every chain to test all units. The comparison of the expected versus the observed response of a unit is performed locally at each unit. Our algorithm provides an order of magnitude speed-up in test time over conventional boundary scan based testing schemes. Further, as the number of chains increases, the test time tends asymptotically toward the optimal. The complete design of the test architecture is also presented.

One of the key factors that has prevented multi-chip modules (MCMs) from gaining mass acceptance in the electronics industry is their high cost. Often contributing to as much as 40% of this cost is the cost of testing the MCMs after they are manufactured. In this paper, we address the problem of testing MCMs fabricated on large area substrates, analogous to the way ICs are manufactured on silicon wafers (this reduces manufacturing cost). Our objective is to reduce the cost of testing MCMs by parallelizing the test process. In this paper we propose a novel relay propagation scheme in which the test stimuli and their correct responses are scanned in an interleaved and pipelined manner into the MCMs. Comparison of the observed and the correct response for each test vector is performed locally at each MCM. It is shown that our scheme results in drastic speedup over conventional boundary scan based testing. We also show that the test time using our testing methodology asymptotically approaches the optimal with the use of larger numbers of test chains.

The design of a cellular automata (CA) based byte error correcting code analogous to an extended Reed-Solomon code has been proposed by Chowdhury et al. (1982, 1985). This code has the same restrictions on error correction as that of an extended R-S code. A new design scheme has been reported for parallel implementation of the CA based SbEC/DbED and DbEC/DbED code that is analogous to the conventional R-S code. Both the encoder and decoder of this code can be efficiently implemented with an array of CA (CAA) with high throughput. The design is ideally suited for high speed memory systems built with byte organized RAM chips. Extension of the scheme to detect/correct a larger number of byte errors has also been reported. Throughput of the decoder to handle tbyte errors (t/spl les/4) can be found to be substantially better than that of a conventional R-S decoder. The proposed decoder provides a simple, modular and cost effective design that is ideally suited for VLSI implementation.

This paper addresses the issue of testing MCMs on large-area substrates. The cost of testing each MCM may be as high as 40% of the total manufacturing cost. It is critical that the test process be parallelized in order that multiple MCMs may be tested for the cost of testing one MCM. With this objective in mind, we propose a distributed probabilistic diagnosis algorithm for MCMs on large-area substrates. Our algorithm performs better than the existing diagnosis algorithms and can correctly identify almost all MCMs even when the yield is very low (35%). Further it provides upto an order of magnitude reduction in test application time as opposed to serial MCM probe test.