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Hemanth Sampath

dblp:13/6346 · DBLP profile ↗
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11ranked-venue papers
4as first author
0since 2021 · last 2008
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 5 · 1 first-authorComputer networks · 3 · 2 first-authorSoftware engineering, systems software and programming languages · 2Graphics, computer vision, multimedia, augmented reality and games · 2 · 1 first-author

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Electronic design automation · 100%
Computer networks
1 paper
Physical-layer communications · 100%

Topics — the 6 heaviest of 6, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Electronic design automation
analog circuit synthesis
0.012004
Fast and accurate parasitic capacitance models for layout-aware · DAC 2004
Electronic design automation › logic synthesis
layout-aware synthesis
0.012004
Fast and accurate parasitic capacitance models for layout-aware · DAC 2004
Physical-layer communications
MIMO
0.012001
Generalized linear precoder and decoder design for MIMO channels using the weighted MMSE criterion · IEEE Trans. Commun. 2001
Physical-layer communications › beamforming › hybrid beamforming
precoder and combiner design
0.012001
Generalized linear precoder and decoder design for MIMO channels using the weighted MMSE criterion · IEEE Trans. Commun. 2001
Electronic design automation › interconnect modeling
parasitic capacitance extraction
0.012004
Fast and accurate parasitic capacitance models for layout-aware · DAC 2004
Physical-layer communications › MIMO
spatial multiplexing
0.012001
Generalized linear precoder and decoder design for MIMO channels using the weighted MMSE criterion · IEEE Trans. Commun. 2001

Methods — techniques the papers use, named apart from their topics

multi-variate linear interpolation · 0.0lookup table · 0.0weighted MMSE · 0.0convex optimization · 0.0
YearPublicationVenuePosition
2008 Field Results on MIMO Performance in UMB Systems
abstract
The paper presents MIMO field performance results observed using a ultra mobile broadband (UMB) testbed network. We evaluate metrics such as antenna correlations and channel condition number to characterize the MIMO channel. Results show that low condition numbers, which are beneficial to MIMO, are prevalent for a majority of the coverage area in our network. We demonstrate that the use of MIMO provides gains of the order of 20-40% over SIMO transmissions. These gains are made possible by the use of cross-polarized transmit antennas and advanced UMB features that allow dynamic MIMO vs. SIMO transmission selection based on channel conditions. These results are obtained in a truly mobile, wireless wide-area deployment, which makes them unique. Our results point to the viability and value of MIMO in future mobile wireless networks.
Harris Teague, Chirag S. Patel, Dhananjay Gore, Hemanth Sampath, Ayman F. Naguib, Tamer Kadous, Alexei Gorokhov, Avneesh Agrawal
VTC Spring4
2006 Dual-polarization versus single-polarization MIMO channel measurement results and modeling
abstract
This paper presents a simple multiple-input-multiple-output (MIMO) channel model that predicts the eigenvalue distribution and hence, the capacity of MIMO systems using vertically polarized and dual-polarized transmit-antenna configurations with dual-polarized receive antennas. The channel model is verified using broadband outdoor channel measurements taken by a 2 x 3 MIMO system in the 2.5 GHz band.
Vinko Erceg, Hemanth Sampath, Severine Catreux-Erceg
IEEE Trans. Wirel. Commun.2
2005 Performance analysis of linear precoding based on field trials results of MIMO-OFDM system
abstract
We use field trial results obtained from a multiple-input multiple-output (MIMO) orthogonal frequency-division multiplexing (OFDM) wireless system with two transmitter and three receiver antennas (2/spl times/3), to first validate the properties of the transmit correlation matrix in a macro-cellular environment. We find that approximately 20% of the locations have well-defined transmit correlation matrices. Furthermore, the eigenvectors of the transmit correlation matrix vary slowly over distance with 60% of the locations having eigenvector variation of less than 1 dB over a distance of 20 m. Next, we quantify the performance of the optimal statistical linear precoding (OSLP) , and statistical one-dimensional (1-D) eigenbeamforming (SEB) based on transmit correlation matrices, and the 1-D eigenbeamforming (EB)-based on perfect channel knowledge at the transmitter. We find that the OSLP and SEB schemes obtain array gain over the Alamouti scheme at lower signal-to-noise ratio (SNR) with a median gain of 2.0 (1.5) dB at the 1.0-(3.5) km cell-radii. However, the SEB scheme (unlike the OSLP scheme) looses diversity order at higher SNR that leads to a performance loss. The EB scheme provides the best performance over the Alamouti scheme, at the expense of increased feedback requirements.
Hemanth Sampath, Vinko Erceg, Arogyaswami Paulraj
IEEE Trans. Wirel. Commun.1
2004 Fast and accurate parasitic capacitance models for layout-aware
abstract
Considering layout effects early in the analog design process is becoming increasingly important. We propose techniques for estimating parasitic capacitances based on look-up tables and multi-variate linear interpolation. These models enable fast and accurate estimation of parasitic capacitances and are very suitable for use in a synthesis flow. A layout aware methodology for synthesis of analog CMOS circuits using these parasitic models is presented. Results indicate that the proposed synthesis system is fast as compared to a layout-inclusive synthesis approach.
Anuradha Agarwal, Hemanth Sampath, Veena Yelamanchili, Ranga Vemuri
DAC2
2004 Accurate Estimation of Parasitic Capacitances in Analog Circuits
abstract
This paper presents efficient and accurate techniques for modeling parasitic capacitances in analog CMOS circuits. A layout aware synthesis flow using these parasitic models has been proposed. The fast parasitic estimation process replaces the time consuming steps of layout generation and extraction during synthesis. Results indicate that these models are extremely fast and accurate.
Anuradha Agarwal, Hemanth Sampath, Veena Yelamanchili, Ranga Vemuri
DATE2
2004 Fast, Layout-Inclusive Analog Circuit Synthesis using Pre-Compiled Parasitic-Aware Symbolic Performance Models
abstract
We present a new methodology for fast analog circuit synthesis, based on the use of parameterized layout generators and symbolic performance models (SPMs) in the synthesis loop. Fast layout generation is achieved by using efficient parameterized procedural layout generators. Fast performance estimation is achieved by using pre-compiled SPMs, stored as efficient DDD-like structures called element coefficient diagrams. Techniques have been developed to include layout geometry effects in the SPMs. The accuracy and efficiency of the parasitic inclusion technique as well as the proposed methodology have been demonstrated by comparisons to traditional synthesis methods. The proposed methodology is used for the synthesis of opamps and filters and is demonstrated to achieve effective performance closure.
Mukesh Ranjan, Wim Verhaegen, Anuradha Agarwal, Hemanth Sampath, Ranga Vemuri, Georges Gielen
DATE4
2004 A high level language for pre-layout extraction in parasite-aware analog circuit synthesis
abstract
This paper presents a high-level language MSL, for the specification of parameterized, topology-specific circuit extractors. Upon compilation, the MSL program yields an executable module which generates the extracted circuit containing parasitics, passive and active devices when given specific sizes. In contrast to traditional post-layout extraction, this is done without ever generating a layout. We call this pre-layout extraction. Pre-layout extraction is much faster than post-layout extraction and is highly suited for use in layout-aware circuit sizing programs. MSL can also be used for the specification of parameterized layout generators. Thus, although a concrete layout is never generated during pre-extraction, the extracted circuit is very much influenced by the symbolic placement and routing specified in the layout generation part of the MSL program. This ensures that the pre-layout extraction process yields the same results as post-layout extraction. Being a high-level language based approach, users can tune pre-layout extraction to a desired level of accuracy by modeling selected parasitics and ignoring others. This ability helps further speed up the circuit sizing process up to a factor varying from 2.5 to 4.5 compared to layout-inclusive synthesis methodologies.
Raoul F. Badaoui, Hemanth Sampath, Anuradha Agarwal, Ranga Vemuri
ACM Great Lakes Symposium on VLSI2
2003 MSL: A High-Level Language for Parameterized Analog and Mixed Signal Layout Generators
Hemanth Sampath, Ranga Vemuri
VLSI-SOC1
2002 Linear precoders and decoders designs for MIMO frequency selective channels
abstract
In this paper we derive and compare designs for the optimal linear precoderes to be used in transmissions over frequency selective multiple-input multiple-output (MIMO) channels. We assume as alternative design constraints the average transmit power and the peak power. The design criteria are scalable with respect to the number of antennas, size of the coding block and transmit average/peak power. The solutions are shown to convert in both cases the MIMO channel with memory into a set of parallel independent fiat fading subchannels, regardless of the design criterion, while appropriate power/bits loading on the sub-channels is the specific signature of the different designs.
Anna Scaglione, Petre Stoica, Sergio Barbarossa, Hemanth Sampath
ICASSP4
2001 Generalized linear precoder and decoder design for MIMO channels using the weighted MMSE criterion
abstract
We address the problem of designing jointly optimum linear precoder and decoder for a MIMO channel possibly with delay-spread, using a weighted minimum mean-squared error (MMSE) criterion subject to a transmit power constraint. We show that the optimum linear precoder and decoder diagonalize the MIMO channel into eigen subchannels, for any set of error weights. Furthermore, we derive the optimum linear precoder and decoder as functions of the error weights and consider specialized designs based on specific choices of error weights. We show how to obtain: (1) the maximum information rate design; (2) QoS-based design (we show how to achieve any set of relative SNRs across the subchannels); and (3) the (unweighted) MMSE and equal-error design for fixed rate systems.
Hemanth Sampath, Petre Stoica, Arogyaswami Paulraj
IEEE Trans. Commun.1
1999 Space-time processing TDMA wireless testbed
abstract
The paper describes the architecture of the Stanford University (SU) TDMA standalone testbed. The testbed was developed to evaluate space-time processing (STP) algorithms for diversity, co-channel interference (CCI) and intersymbol interference (ISI) mitigation, array gain and space-time coding. It operates in both uplink and downlink modes and uses a hybrid (combining a real and simulated) channel environment. A description of transmit and receive schemes implemented on the testbed is presented.
Hemanth Sampath, Arogyaswami Paulraj
ICASSP1