Strong Physical Unclonable Functions (PUFs) are critical for lightweight authentication in the Internet of Things (IoT). However, traditional Strong PUF designs are susceptible to advanced Machine Learning (ML) modeling attacks. In this article, we propose a novel modeling-attack-resilient Strong PUF architecture that transforms the challenge-response mapping from a statically approximable function into a mathematically rigorous Keyed Pseudo-Random Function (Keyed-PRF). The proposed architecture features two core innovations: a Sponge-Based Configuration Mechanism (SCM) that utilizes reliable Weak PUFs to dynamically configure the feedback polynomial of a Linear Feedback Shift Register (LFSR), effectively creating a device-specific secret key; and a Response-Modulated State Evolution Mechanism (RM-SEM), where the instantaneous physical responses of the underlying Arbiter PUF determine the evolution step size of the LFSR. This creates a deep temporal feedback loop that transforms the system into a Hidden Markov Model (HMM), blocking gradient-based learning strategies. We also introduce a reliability screening strategy based on a strict bit-error-rate threshold to ensure stability. Experimental results on Xilinx Artix-7 FPGAs demonstrate that the proposed PUF maintains a prediction accuracy of approximately 50% against four mainstream modeling attacks even with 1 million training Challenge-Response Pairs (CRPs). Furthermore, the design exhibits excellent uniformity, uniqueness, and reliability, achieving these security properties with minimal hardware overhead.

As a core component in the field of information security, the true random number generator (TRNG) produces high-entropy random numbers by extracting unpredictable noise from the physical environment, exhibiting nonreproducibility and resistance to prediction. To address the challenges posed by interference in high-speed systems, maintaining stable throughput and entropy sources for TRNG, this article proposes an optimized TRNG that utilizes chaotic interference to refresh the cellular automata (IRCA) iterative algorithm. The IRCA-TRNG utilizes a self-timed ring oscillator (STR) and jitter to perturb the operation of chaotic cellular automata (CA) cells, achieving a high-throughput TRNG. The generated random sequences have successfully passed NIST SP800-22, TESTU01, NIST SP800-90B, and AIS-31 tests. A throughput of 1040 Mb/s has been achieved on Xilinx Artix-7 and PYNQ-K2 series development boards. Compared with the state-of-the-art works, the proposed TRNG demonstrates significant advantages in resource utilization and performance quality factors.