Ultra-dynamic voltage scaling (UDVS) is a popular trade-off technique between delay and power performance. However, voltage scaling will degrade the radiation-aware reliability of traditional latch obviously. In addition, although the shrinkage of feature sizes results in the reduction of latch area, the occurrence possibility of double node upset (DNU) and triple node upset (TNU) events are increasing. Achieving a good balance among delay, power, area and reliability performance is becoming an important issue in the design of radiation-hardened latches, especially considering the coming commercial aerospace applications. Therefore, this paper proposes a TNU self-recoverable latch with wide voltage range (TRLW), which is low overhead and very suitable for UDVS technique. The TRLW latch is mainly composed of two completely interlocking triangle structures, and is able to self-recover from any possible TNU event. Clock-gated isolated cells are skillfully utilized to avoid current conflict. Meanwhile, six transmission gates are carefully integrated into TRLW latch to reduce the propagation delay$\textit{t}_{d2q}$and critical path delay$\textit{t}_{crit}$. Accordingly, the overall performance of TRLW latch is always excellent from normal voltage to near-threshold voltage (NTV). Simulation results based on 28nm CMOS process show that TRLW latch can achieve complete SNU, DNU and TNU self-recovery in all possible cases, and the soft error rate of TRLW latch only raises by 4.6$\%$when the supply voltage is decreased from 0.9 V to 0.3 V. Moreover, compared with the other reported TNU self-recovery latches, TRLW latch consistently achieves the minimum delay, power, area and delay-power-area product (DPAP) under different process, voltage and temperature (PVT) conditions, and obtains average reductions of 3.43$\times$, 3.03$\times$, 2.66$\times$, 1.40$\times$and 10.83$\times$for$\textit{t}_{d2q}$,$\textit{t}_{crit}$, power, area and DPAP when operating from 0.5 V to 1.0 V.

As the feature size of integrated circuits (ICs) continues to shrink, radiation-induced multiple bit upsets (MBUs) become more frequent than single bit upsets (SBUs) in nanometer ICs. However, it is still very difficult and time consuming to evaluate the sensitivity of digital very large scale ICs (VLSIs) to MBUs. To accelerate MBU evaluation, an MBU emulation platform is proposed via hardware-software co-design approach in this paper. Based on the proposed layout back-annotation technique, the platform back-annotates information of adjacent flip-flop (FF) cells in layout-level physical gate-level (PGL) netlist to the matching register cells in register transfer level (RTL) code, and is able to perform fast and accurate MBU emulation for layout-level digital VLSIs. Finally, several experiments on four different digital designs are implemented with Xilinx Zynq-7000 FPGA, and the correctness and effectiveness of the proposed MBU emulation platform are verified by these experiments.

As the communication infrastructure utilized by Tiled Chip Multicore Processors (TCMP), Network-on-Chip (NoC) has been subject to serious security vulnerabilities due to hardware Trojans (HTs) concealed in potentially insecure 3PIPs. To satisfy the need for secure NoCs, it is vital to model potential attacks and analyze their impacts on NoC performance. This paper proposes a novel and covert HT model called Spotlight targeting specific victim node in XY-routing NoC to optimize the attacking effect. By inserting Trojans into special nodes and modifying the arbiters of input ports within the switch allocator of router, packets flowing to the victim node are unfairly treated causing considerable latency. As a result, the HT effectively degrades the transmission of packets while having a subtle impact on other NoC performance. The proposed HT is inserted into Garnet 2.0 of Gem5 simulator for performance evaluation. Experimental results indicate that the Spotlight attack increased the average delay of target packets by 12.16 cycles. Compared to some DoS attacks, the proposed Trojan affected packet transmission with fewer packets, causing minimal fluctuates in NoC metrics such as average latency. And the area and power overheads are only 0.94% and 0.11%, respectively.

As the feature size of the nanoscale CMOS keeps scaling down, the charge sharing effect is becoming more and more prominent, and the occurrence possibility of the triple-node upset (TNU) increases obviously. Therefore, this article proposes a TNU-tolerant latch with low overhead (TTLL), which achieves a good tradeoff between reliability and design overhead. The high reliability against the TNU of the TTLL latch mainly depends on the structure of two interlocking rings and the output recovery module. Meanwhile, the clock-gated and high-speed path technology is utilized cleverly to optimize power consumption and propagation delay performance. Simulation results in the 28-nm CMOS process show that the TTLL latch has the minimum delay-power-area product (DPAP) among all reported latches for a wide range of operating conditions and under typical conditions achieves on average$1.11\times $,$10.34\times $, and$18.44\times $reductions in power, delay, and DPAP, respectively.