The number theoretic transform (NTT), which can reduce the computational complexity of polynomial multiplication, has been widely used to accelerate cryptographic algorithms. However, due to the significant computational data volume, the limited memory bandwidth of chips limits the effectiveness of massive parallel computation in achieving high performance. In addition, the accelerator must flexibly adapt to variable parameters for diverse encryption scenarios, leading to a nonlinear growth in hardware resources and underutilization of the computation engines. Therefore, this article proposes a scalable 2-D constant-geometry (2-D CG) accelerator designed to fully utilize butterfly units (BFUs) and avoid a drastic increase in hardware resources. The proposed architecture reduces high memory bandwidth requirements by compressing BFUs from the vertical to the horizontal direction, thereby eliminating BFU idle time waiting for data transmission. We then propose a scalable 2-D CG design that performs a constant number of data access patterns within each stage to prevent the dramatic increase in complexity as the architecture scales. In addition, we propose a channel reconfigurable Barrett (CR_Barrett) architecture that computes multiple small-bitwidth modular multiplications (MMs) in parallel, ensuring that all computation engines are actively utilized. Finally, we designed and verified the proposed 2-D CG NTT accelerator on a field-programmable gate array (FPGA). Compared to state-of-the-art works, the 2-D CG achieves$1.47\times $to$7.17\times $higher throughput per slice (TPS) for scalable architectures and$2.02\times $to$6.41\times $higher TPS for runtime configurable architectures.

Sparse convolutional neural networks (SCNNs) which can prune trivial parameters in the network while maintaining the model accuracy has been proved to be an attractive approach to alleviate the heavy computation of convolutional neural networks (CNNs). However, the invalid data resulting from sparse patterns leads to unnecessary and irregular computation workload, which challenges the efficiency of the underlying hardware accelerators. Therefore, this article proposes an SCNN inference accelerator, which can deal with the imbalanced workload both intra- and interprocessing element (PE). A valid weight encoding (VWE) scheme is proposed to compress sparse weights into dense ones to alleviate the load imbalance intra-PE. Leveraging the VWE scheme, a randomized load rearrangement (RLR) method is proposed to dynamically schedule convolution kernels with similar sparsity into the same computation batch to alleviate the load imbalance inter-PEs. In addition, to reduce off-chip memory accesses, a recurrent weight stationary (RWS) dataflow is proposed, which adopts a small-batch and multichannel strategy to stack data from multiple channels within one off-chip access and let them compute simultaneously thereby enabling efficient reuse of on-chip data. Based on the proposed scheme, an efficient SCNN inference accelerator has been designed and verified on the field-programmable gate array (FPGA). Compared with state-of-the-art works, our design achieves$1.16\times $to$2.77\times $higher digital signal processors (DSPs) efficiency and$1.75\times $to$15\times $higher logic efficiency.

This brief proposes a scalable multistage and multipath architecture for variable number-theoretic transform (NTT). The proposed architecture adopts multiple parallel paths, each of which uses cascaded radix-2 butterfly units (BFUs). The radix-2 scheme simplifies the control logic and the cascaded BFU structure reduces the amount of RAM banks and the frequency of memory accesses. Moreover, a conflict-free and hardware-friendly in-place memory mapping scheme is proposed to ease the adaption to multiple paths, letting it be scalable for various throughputs. Compared with state-of-the-art works, the proposed architecture uses fewer resources and has better area-time product performance without penalty in throughput.

The new generation of artificial intelligence (AI) technology will play an important role in promoting the digitalization, informatization and intelligence of the future power grid due to its high-dimensional state intelligent perception and rapid decision-making capabilities. However, its inherent shortcomings such as poor interpretability and fragility also limit the further application of AI technology in power systems. This paper first introduces hybrid-augmented intelligence (HAI) technology and its application development in the fields of autonomous driving and industrial robots. Combining the characteristics of the power system and AI technology, the requirements of the power system for HAI are analyzed and summarized. Secondly, the key technologies involved in human-machine collaborative HAI are analyzed in terms of data processing, model training and model application. On this basis, the application of HAI technology in typical scenarios such as power flow section regulation is designed and analyzed, which provides reference for subsequent engineering applications. Finally, the challenges faced by the application of HAI in power systems are analyzed and prospected, aiming to promote and enrich the development of basic theories and key technologies of hybrid intelligence in power systems.

In this paper, we aim to illustrate the concept of mutually trustworthy human-machine knowledge automation (HM-KA) as the technical mechanism of hybrid augmented intelligence (HAI) based complex system cognition, management, and control (CMC). We describe the historical development of complex system science and analyze the limitations of human intelligence and machine intelligence. The need for using human-machine HAI in complex systems is then explained in detail. The concept of “mutually trustworthy HM-KA” mechanism is proposed to tackle the CMC challenge, and its technical procedure and pathway are demonstrated using an example of corrective control in bulk power grid dispatch. It is expected that the proposed mutually trustworthy HM-KA concept can provide a novel and canonical mechanism and benefit real-world practices of complex system CMC.

The resilience of a power system refers to its ability to resist and recover from multiple physical failures under extreme operation conditions. In this paper, we study the power grid resilience considering different time scales of recovery strategies and propose a method for identifying critical elements whose physical damage can significantly degrade the resilience of a power system. The maximum power supply (MPS) of the remaining network containing the elements that are not physically damaged is obtained and used to indicate the resilience performance of the system. We identify the critical elements in the grid by iteratively selecting and removing the link with the lowest MPS. We do simulations in the IEEE 118 Bus case to evaluate the grid resilience under various extremes and test the proposed strategy. Simulation results validate the efficacy of our proposed method in the identification of critical elements.

Accurate software defect prediction could help software practitioners allocate test resources to defect-prone modules effectively and efficiently. In the last decades, much effort has been devoted to build accurate defect prediction models, including developing quality defect predictors and modeling techniques. However, current widely used defect predictors such as code metrics and process metrics could not well describe how software modules change over the project evolution, which we believe is important for defect prediction. In order to deal with this problem, in this paper, we propose to use the Historical Version Sequence of Metrics (HVSM) in continuous software versions as defect predictors. Furthermore, we leverage Recurrent Neural Network (RNN), a popular modeling technique, to take HVSM as the input to build software prediction models. The experimental results show that, in most cases, the proposed HVSM-based RNN model has significantly better effort-aware ranking effectiveness than the commonly used baseline models.