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Andrew Brownsword

dblp:13/932 · DBLP profile ↗
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4ranked-venue papers
1as first author
0since 2021 · last 2011
0009-0006-8073-681XORCID · corroborated

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 2Software engineering, systems software and programming languages · 2 · 1 first-author

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
2 papers
Parallel and multicore computing · 60% Distributed systems · 24% GPUs and heterogeneous computing · 16%
Software engineering, system software, and programming languages
1 paper
Concurrent programming · 100%

Topics — the 10 heaviest of 10, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Parallel and multicore computing › transactional memory
conflict detection
0.112011
Hardware transactional memory for GPU architectures · MICRO 2011
Distributed systems › workflow management
dependency management
0.112011
Synchronization via scheduling: techniques for efficiently managing shared state · PLDI 2011
GPUs and heterogeneous computing
GPU transactional memory
0.112011
Hardware transactional memory for GPU architectures · MICRO 2011
Parallel and multicore computing › transactional memory
hardware transactional memory
0.112011
Hardware transactional memory for GPU architectures · MICRO 2011
Parallel and multicore computing
parallel programming models
0.112011
Synchronization via scheduling: techniques for efficiently managing shared state · PLDI 2011
Distributed systems › distributed coordination
shared state management
0.112011
Synchronization via scheduling: techniques for efficiently managing shared state · PLDI 2011
Parallel and multicore computing › task scheduling
task graph scheduling
0.112011
Synchronization via scheduling: techniques for efficiently managing shared state · PLDI 2011
Parallel and multicore computing
transactional memory
0.112011
Hardware transactional memory for GPU architectures · MICRO 2011
Concurrent programming
synchronization
0.012011
Synchronization via scheduling: techniques for efficiently managing shared state · PLDI 2011
GPUs and heterogeneous computing › GPU microarchitecture
SIMT architecture
0.012011
Hardware transactional memory for GPU architectures · MICRO 2011

Methods — techniques the papers use, named apart from their topics

task graph model · 0.2speculative validation · 0.1bloom filter validation · 0.1
YearPublicationVenuePosition
2011 Hardware transactional memory for GPU architectures
abstract
Graphics processor units (GPUs) are designed to efficiently exploit thread level parallelism (TLP), multiplexing execution of 1000s of concurrent threads on a relatively smaller set of single-instruction, multiple-thread (SIMT) cores to hide various long latency operations. While threads within a CUDA block/OpenCL workgroup can communicate efficiently through an intra-core scratchpad memory, threads in different blocks can only communicate via global memory accesses. Programmers wishing to exploit such communication have to consider data-races that may occur when multiple threads modify the same memory location. Recent GPUs provide a form of inter-block communication through atomic operations for single 32-bit/64-bit words. Although fine-grained locks can be constructed from these atomic operations, synchronization using locks is prone to deadlock. In this paper, we propose to solve these problems by extending GPUs to support transactional memory (TM). Major challenges include supporting 1000s of concurrent transactions and committing non-conflicting transactions in parallel. We propose KILO TM, a novel hardware TM design for GPUs that scales to 1000s of concurrent transactions. Without cache coherency hardware to depend on, it uses word-level, value-based conflict detection to avoid broadcast communication and reduce on-chip storage overhead. It employs speculative validation using a novel bloom filter organization to increase transaction commit parallelism. For a set of TM-enhanced GPU applications, KILO TM captures 59% of the performance of fine-grained locking, and is on average 128x faster than executing all transactions serially, for an estimated hardware area overhead of 0.5% of a commercial GPU.
Wilson W. L. Fung, Inderpreet Singh, Andrew Brownsword, Tor M. Aamodt
MICRO3
2011 Synchronization via scheduling: techniques for efficiently managing shared state
abstract
Shared state access conflicts are one of the greatest sources of error for fine grained parallelism in any domain. Notoriously hard to debug, these conflicts reduce reliability and increase development time. The standard task graph model dictates that tasks with potential conflicting accesses to shared state must be linked by a dependency, even if there is no explicit logical ordering on their execution. In cases where it is difficult to understand if such implicit dependencies exist, the programmer often creates more dependencies than needed, which results in constrained graphs with large monolithic tasks and limited parallelism.
Micah J. Best, Shane Mottishaw, Craig Mustard, Mark Roth, Alexandra Fedorova, Andrew Brownsword
PLDI6
2009 Searching for Concurrent Design Patterns in Video Games
Micah J. Best, Alexandra Fedorova, Ryan Dickie, Andrea Tagliasacchi, Alex Couture-Beil, Craig Mustard, Shane Mottishaw, Aron Brown, Zhi Feng Huang, Xiaoyuan Xu, Nasser Ghazali, Andrew Brownsword
Euro-Par12
2008 Software Architecture in Game Development
abstract
Summary form only given. Video games have now existed in various forms for over 30 years, and have evolved from humble beginnings into remarkably complex software projects. The ever present emphasis on an immersive audio/visual experience has put game developers in the position of being on the bleeding edge of exploring the performance of modern consumer hardware. This talk will discuss the elements that make up a contemporary video game, the software processes that are involved in development, key challenges, and look at some important design patterns that form the architectural basis.
Andrew Brownsword
WICSA1