Latch clustering is a critical stage to reduce power consumption at cost of timing disruption during a modern SoC design flow. However, most existing latch clustering researches mitigate timing disruptions by indirectly minimizing latch displacement during clustering, which is inaccurate and insufficient for timing closure in the design flow. Further, most researches do not control the amount of inserted clock buffers during clustering, which is the key factor to provide flexibility for timing and power trade-off. To address the two issues above, this paper presents a novel timing-power co-optimized latch clustering framework: we augment an integer linear programming (ILP) formulation of a facility-location allocation (FLA) problem to (1) directly optimize timing with a path-based timing model and (2) accurately control the number of inserted buffers by the FLA formulation for power optimization. We evaluate the framework with a displacement-optimized clustering approach and a state-of-the-art approach. Experimental results show 46% total negative slack timing overhead reduction, and 21% reduction for total power consumption.

A modern field-programmable gate array (FPGA) often contains an ASIC-like clocking architecture which is crucial to achieve better skew and performance. Existing conventional FPGA placement algorithms seldom consider clocking resources, and thus may lead to clock routing failures. To address the special FPGA clocking architecture, this article presents an effective clock-aware placement algorithm for large-scale heterogeneous FPGAs. Our algorithm consists of four major technologies: 1) a combinatorial clock fence region method to effectively reduce the overuse of clocking resources; 2) a smoothed heterogeneous density function to lead heterogeneous blocks to desired sites and a coordinate transformation technique to facilitate CLB cell spreading; 3) a heterogeneous force modulation algorithm to stabilize placement movement and a hierarchical contraction technique to remedy an insufficiency of the multilevel placement framework; and 4) a two-level clock-aware packing and legalization scheme to generate an optimized, clocking-violation-free placement. We evaluate our results based on the ISPD 2017 Clock-Aware Placement Contest benchmark suite. Compared with the state-of-the-art placers, the experimental results show that our algorithm achieves the best-routed wirelength.

A placer without considering modern technology and region constraints could generate solutions with irresolvable detailed-routing (DR) violations or even illegal solutions. This paper presents a high-quality placement algorithm to satisfy technology and region constraints and optimize DR routability with five major techniques: 1) a clustering algorithm followed by two-round quadratic placement to obtain an initial placement satisfying region constraints; 2) a novel density control technique to handle prefixed architectures and minimize global routing congestions; 3) an analytical placement algorithm with new wirelength and density models to consider region constraints; 4) a dynamic penalty increment strategy that reduces wirelength increments during global placement; and 5) a legalization algorithm that preserves the solution quality of global placement while satisfying technology and region constraints. Compared with the winning teams of the ISPD 2015 Blockage-Aware Detailed Routing-Driven Placement Contest and recent works, our placer achieves the best overall score and DR results.

Extracting similar datapath bit slices which handle highly parallel bit operations can help a modern placer to obtain better solutions for datapath-oriented designs. A current state-of-the-art datapath bit slicing method achieves the best extraction results using a network-flow-based algorithm. However, this work has two major drawbacks: (1) it extracts only a limited number of bit slices for datapaths with different I/O widths, which are commonly seen in real designs, and (2) it does not consider bit-slice similarity, which is an important feature for placement considering datapaths. To remedy these drawbacks, we present (1) a balanced bipartite edge-cover algorithm to fully slice a datapath with different I/O widths, and (2) a simulated annealing scheme to further improve bit-slice similarity, while maintaining fully-sliced structures. Compared with the state-of-the-art work, experimental results show that our slicing algorithm extracts more bit slices with similar structures, and helps a leading academic placer achieve averagely 5% smaller routed wirelength. The results also validate the high correlation between datapaths and structure regularity/similarity.

A modern FPGA often contains an ASIC-like clocking architecture which is crucial to achieve better skew and performance. Existing conventional FPGA placement algorithms seldom consider clocking resources, and thus may lead to clock routing failures. To address the special FPGA clocking architecture, this paper presents a novel clock-aware placement algorithm for large-scale heterogeneous FPGAs. Our algorithm consists of three major stages: (1) a nonlinear global placement framework with clock fence region construction, (2) a clock-aware packing scheme, and (3) clock-aware legalization and detailed placement. We evaluate our results based on the 2017 ISPD Clock-Aware Placement Contest benchmark suite. Compared with the top three winners, the results show that our algorithm achieves the best overall routed wirelength. On average, our algorithm outperforms the top-3 winners by 3.6%, 7.5%, and 12.9% in routed wirelength, respectively.

As interconnects dominate circuit performance in modern chip designs, placement becomes an essential stage in optimizing timing. Recent timing-driven placement (TDP) techniques focus mainly on optimizing late slack rather than early slack. This paper presents a TDP algorithm to improve the early slack while preserving an optimized late slack. The preservation is achieved by accurately predicting optimal Steiner tree topologies after each move in our TDP algorithm. An optimality-preserving pruning scheme for each move is proposed to speed up the optimization process, without sacrificing the solution quality. Experimental results show that our algorithm can substantially improve the early slacks and the overall quality scores of the top-2 winning placers of the 2015 ICCAD Incremental Timing-Driven Placement Contest, while preserving their late slacks.

Due to the significant mismatch between global-routing congestions estimated during placement and the resulting design-rule violations in detailed routing, considering both global and detailed routability during placement is of particular importance for modern circuit designs. This paper presents an analytical standard-cell placement algorithm to optimize detailed routability with three major techniques: (1) A routability-driven wirelength model that directly minimizes routing congestion and wirelength simultaneously with no additional computational overhead in global placement. (2) A detailed-routability-aware whitespace allocation technique in legalization. (3) A multi-stage congestion-aware cell spreading method in detailed placement. Compared with the participating teams of the 2014 ISPD Detailed-Routing-Driven Placement Contest and a state-of-the-art routability-driven placer, our placer achieves the best quality in both detailed-routing violation and wirelength scores.

A placer without considering modern technology and region constraints could generate solutions with irresolvable detailed-routing violations or even illegal solutions. This paper presents a high-quality placement algorithm to satisfy technology and region constraints and optimize detailed-routing routability with three major techniques: (1) a clustering algorithm followed by two-round quadratic placement to obtain an initial placement satisfying region constraints, (2) an analytical placement algorithm with new wirelength and density models to consider region constraints, and (3) a legalization algorithm that preserves the solution quality of global placement while satisfying technology/region constraints. Compared with the winning teams of the ISPD 2015 Blockage-Aware Detailed Routing-Driven Placement Contest, our placer achieves the best overall score and detailed-routing results.

We present a new floorplan representation, called circular-packing trees (CP-trees), for the problem of macro placement. Our CP-trees can flexibly pack movable macros toward corners or pre-placed macros along chip boundaries circularly to optimize macro positions/orientations for better wirelength and routing congestion. Unlike previous macro placers that often consider only the interconnections among macros, we develop a routability-aware wirelength model to fast estimate the wirelength among macros and standard cells and to consider macro porosity effects for better routability. Compared with leading academic mixed-size placers, experimental results show that our algorithm can achieve the shortest routed wirelength for industrial benchmarks.

A wirelength-driven placer without considering routability could introduce irresolvable routing-congested placements. Therefore, it is desirable to develop an effective routability-driven placer for modern mixed-size designs employing hierarchical methodologies for faster turnaround time. In this paper, we propose a novel routability-driven analytical placement algorithm for hierarchical mixed-size circuit designs. This paper presents a novel design hierarchy identification technique to effectively identify design hierarchies and guide placement for better wirelength and routability. The proposed algorithm optimizes routability from four major aspects: 1) narrow channel handling; 2) pin density; 3) routing overflow optimization; and 4) net congestion optimization. Routability-driven legalization and detailed placement are also proposed to further optimize routing congestion. Compared with the participating teams for the 2012 ICCAD Design Hierarchy Aware Routability-driven Placement Contest, our placer can achieve the best quality (both the average overflow and wirelength) and the best overall score (by additionally considering running time).

A wirelength-driven placer without considering routability could introduce irresolvable routing-congested placements. Therefore, it is desirable to develop an effective routability-driven placer for modern mixed-size designs employing hierarchical methodologies for faster turnaround time. This paper presents a novel two-stage technique to effectively identify design hierarchies and guide placement for better wirelength and routability. To optimize wirelength and routability simultaneously during placement, a new analytical net-congestion-optimization technique is also proposed. Compared with the participating teams for the 2012 ICCAD Design Hierarchy Aware Routability-driven Placement Contest, our placer can achieve the best quality (both the average overflow and wire-length) and the best overall score (by additionally considering running time).