Demo Data from EDBT 2026 / reviewers in the wild / expert
Adithya Parandhaman
dblp:130/1345
· DBLP profile ↗
1ranked-venue papers
0as first author
0since 2021 · last 2013
—ORCID · none
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 1
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
1 paper |
Hardware reliability and fault tolerance · 56% Integrated circuit design · 28% Electronic design automation · 17% |
Topics — the 5 heaviest of 5, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Integrated circuit design
low-power circuit design |
0.2 | 1 | 2013 | Relax-and-retime: a methodology for energy-efficient recovery based design · DAC 2013 |
Hardware reliability and fault tolerance › error recovery
recovery-based design |
0.2 | 1 | 2013 | Relax-and-retime: a methodology for energy-efficient recovery based design · DAC 2013 |
Hardware reliability and fault tolerance › processor reliability
timing error recovery |
0.2 | 1 | 2013 | Relax-and-retime: a methodology for energy-efficient recovery based design · DAC 2013 |
Electronic design automation
logic synthesis |
0.0 | 1 | 2013 | Relax-and-retime: a methodology for energy-efficient recovery based design · DAC 2013 |
Electronic design automation › physical design
timing optimization |
0.0 | 1 | 2013 | Relax-and-retime: a methodology for energy-efficient recovery based design · DAC 2013 |
Methods — techniques the papers use, named apart from their topics
voltage overscaling · 0.2retiming · 0.2dual-vth cells · 0.2
| Year | Publication | Venue | Position |
|---|---|---|---|
| 2013 | Relax-and-retime: a methodology for energy-efficient recovery based designabstractRecovery based design (RBD) is a promising approach for the design of energy-efficient circuits under variations. RBD instruments circuits with mechanisms to identify and correct timing violations, thereby allowing reduced guard bands or design margins. In addition, RBD enables aggressive voltage overscaling to a point where timing errors occur even under nominal conditions. A major barrier to the widespread adoption of RBD is that traditional design practices and synthesis tools result in circuits with so-called"path walls", leading to an explosion in the number of timing errors beyond a certain critical operating voltage. To alleviate this effect, previous techniques focused on combinational circuit optimizations such as sizing, use of dual Vth cells, re-structuring, etc. to favorably reshape the path delay distribution. However, these techniques are limited by the inherent sequential structure of the circuit, which defines the boundaries of the combinational logic. Shankar Ganesh Ramasubramanian, Swagath Venkataramani, Adithya Parandhaman, Anand Raghunathan |
DAC | 3 |