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Brennan Cozzens

dblp:130/1373 · DBLP profile ↗
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1ranked-venue papers
0as first author
0since 2021 · last 2013
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 1

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Processor architecture and microarchitecture · 70% Hardware reliability and fault tolerance · 30%

Topics — the 5 heaviest of 5, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Processor architecture and microarchitecture
instruction scheduling		 0.212013
Efficiently tolerating timing violations in pipelined microprocessors · DAC 2013
Processor architecture and microarchitecture › out-of-order execution
out-of-order pipeline		 0.212013
Efficiently tolerating timing violations in pipelined microprocessors · DAC 2013
Processor architecture and microarchitecture › pipelining
pipelined processor		 0.212013
Efficiently tolerating timing violations in pipelined microprocessors · DAC 2013
Hardware reliability and fault tolerance
timing error tolerance		 0.212013
Efficiently tolerating timing violations in pipelined microprocessors · DAC 2013
Hardware reliability and fault tolerance
soft errors		 0.012013
Efficiently tolerating timing violations in pipelined microprocessors · DAC 2013

Methods — techniques the papers use, named apart from their topics

instruction scheduling · 0.2
YearPublicationVenuePosition
2013 Efficiently tolerating timing violations in pipelined microprocessors
abstract
Early prediction of an upcoming timing violation presents a tremendous opportunity to mask the performance overhead of tolerating these faults. In this paper, we explore several techniques for optimizing instruction scheduling in an Out-of-Order pipeline, exploiting this new perspective in robust system design. Compared to recently proposed stall based techniques for tolerating predictable timing violations, we demonstrate a massive reduction in performance overhead, while supporting correct execution in faulty environments (64--97% across different benchmarks).
Koushik Chakraborty, Brennan Cozzens, Sanghamitra Roy, Dean Michael Ancajas
 DAC2