MOTIVATION: Reconstructing and analyzing all blood vessels throughout the brain is significant for understanding brain function, revealing the mechanisms of brain disease, and mapping the whole-brain vascular atlas. Vessel segmentation is a fundamental step in reconstruction and analysis. The whole-brain optical microscopic imaging method enables the acquisition of whole-brain vessel images at the capillary resolution. Due to the massive amount of data and the complex vascular features generated by high-resolution whole-brain imaging, achieving rapid and accurate segmentation of whole-brain vasculature becomes a challenge. RESULTS: We introduce HP-VSP, a high-performance vessel segmentation pipeline based on deep learning. The pipeline consists of three processes: data blocking, block prediction, and block fusion. We used parallel computing to parallelize this pipeline to improve the efficiency of whole-brain vessel segmentation. We also designed a lightweight deep neural network based on multi-resolution vessel feature extraction to segment vessels at different scales throughout the brain accurately. We validated our approach on whole-brain vascular data from three transgenic mice collected by HD-fMOST. The results show that our proposed segmentation network achieves the state-of-the-art level under various evaluation metrics. In contrast, the parameters of the network are only 1% of those of similar networks. The established segmentation pipeline could be used on various computing platforms and complete the whole-brain vessel segmentation in 3 h. We also demonstrated that our pipeline could be applied to the vascular analysis. AVAILABILITY AND IMPLEMENTATION: The dataset is available at http://atlas.brainsmatics.org/a/li2301. The source code is freely available at https://github.com/visionlyx/HP-VSP.

Consolidated server racks are quickly becoming the standard infrastructure for engineering, business, medicine, and science. Such servers are still designed much in the way when they were organized as individual, distributed systems. Given that many fields rely on big-data analytics substantially, its cost-effectiveness and performance should be improved, which can be achieved by flexibly allowing resources to be shared across nodes. Here we describe Venice, a family of data-center server architectures that includes a strong communication substrate as a first-class resource. Venice supports a diverse set of resource-joining mechanisms that enables applications to leverage non-local resources efficiently. We have constructed a hardware prototype to better understand the implications of design decisions about system support for resource sharing. We use it to measure the performance of at-scale applications and to explore performance, power, and resource-sharing transparency tradeoffs (i.e., how many programming changes are needed). We analyze these tradeoffs for sharing memory, accelerators, and NICs. We find that reducing/hiding latency is particularly important, the chosen communication channels should match the sharing access patterns of the applications, and of which we can improve performance by exploiting inter-channel collaboration.

In this work, we implement an ARMv8 function and performance simulator based on gem5 infrastructure, which is the first open source ARMv8 simulator. All the ARMv8 A64 instructions other than SIMD are implemented using gem5 ISA description language. The ARMv8 simulator supports multiple CPU models, multiple memory systems, and McPAT power model.