Ronghua Ni

dblp:130/2477 · DBLP profile ↗
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5ranked-venue papers
0as first author
5since 2021 · last 2026
0009-0009-3686-7785ORCID · verified

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 5 · 5 since 2021
YearPublicationVenuePosition
2026 A 4x106 Gb/s PAM4 Current-Reuse VCSEL Driver with a High-Bandwidth VGA in 130 nm BiCMOS
Wei Chen 0176, Minhao Li, Pisen Zhou, Patrick Chiang 0001, Ronghua Ni
ISCAS8
2026 A 0.1-V Transformer-Based Class-D VCO Achieving 0.9-V Output Swing and >193.8-dBc/Hz FoM at 10-MHz Offset
Chuanhai Gao, Xiaoyue Cai, Xiaohua Yu, Ronghua Ni
ISCAS5
2026 A Quad-Core Series-Resonance VCO Enabled by Circular Lsecondary and Stacked Lprimary Achieving 198.9-dBc/Hz FoM at 10MHz
Dong Pu, Xiaohua Yu, Ronghua Ni
ISCAS4
2026 Design of Symmetric Transformer-Based Quadrature Couplers
Jiayu You, Ronghua Ni, Xiaohua Yu
ISCAS3
2025 An Ultra-Low Power 915 MHz LO with Adaptive Frequency Calibration for IoT Wake-Up Receivers
abstract
This paper presents an ultra-low power 915 MHz Local Oscillator (LO) with adaptive frequency calibration algorithm for IoT Wake-Up Receivers (WURs). The proposed algorithm can adaptively adjust and minimize the calibration time of each bit oscillator tuning word (OTW) as well as the number of OTWs that require re-calibration after open-loop time. These two features help reducing the average LO power consumption by minimizing the closed-loop frequency calibration time. The duty cycle of the closed-loop time can also be adjusted flexibly to further reduce the average LO power consumption at a given frequency stability requirement. Fabricated in 40-nm CMOS, this proposed algorithm reduces the frequency calibration time from 108 μs to 42 μs, achieving a time reduction of 61%. An average LO power consumption of 93 μW at a 5% closed-loop time duty cycle is measured with a frequency accuracy of 120 ppm.
Xianhong Xiu, Tian Huang, Qianhui Li, Hao Min, Xiaohua Yu, Ronghua Ni
ISCAS7