ABSTRACT Heterogeneous architectures are vastly used in various high performance computing systems from IoT‐based embedded architectures to edge and cloud systems. Although heterogeneous architectures with cooperation of CPUs and GPUs and unified address space are increasingly used, there are still a lot of open questions and challenges regarding the design of these architectures. For evaluation, validation and exploration of next generation of heterogeneous CPU–GPU architectures, it is essential to use unified heterogeneous simulators for analyzing the execution of CPU–GPU workloads. This article presents a systematic review on challenges of heterogeneous CPU–GPU architectures with covering a diverse set of literatures on each challenge. The main considered challenges are shared resource management, network interconnections, task scheduling, energy consumption, and programming model. In addition, in this article, the state‐of‐the‐art of heterogeneous CPU–GPU simulation platforms is reviewed. The structure and characteristics of five cycle‐accurate heterogeneous CPU–GPU simulators are described and compared. We perform comprehensive discussions on the methodologies and challenges of designing high performance heterogeneous architectures. Moreover, for developing efficient heterogeneous CPU–GPU simulators, some recommendations are presented.

Summary High performance system‐on‐chip (SoCs) designs have led to high‐density integrated circuits using field programmable gate arrays (FPGAs) for rapid prototyping and reconfigurable digital circuits. Using FPGA reconfigurability, it is possible to design a configurable network‐on‐chip (NoC) for different applications. NoC architectures provide efficient communication infrastructures for implementing very large SoCs. In this article, we propose HiFMP, a high‐performance FPGA‐based multicrossbar prioritized NoC router. The aim followed by the proposed router is designing a low‐power NoC router with high performance in terms of energy‐efficiency, network throughput, area, and latency for efficient FPGA realization. HiFMP is a parameterizable router, and is effectively used for an FPGA‐based NoC with mesh topology. Performance evaluations include network‐level analysis and hardware exploration; the results demonstrate the effectiveness and high performance of HiFMP in terms of latency, throughput, power consumption, and area, comparing with the existing related architectures.

General purpose hybrid dataflow/von-Neumann architectures are gaining attraction as effective parallel platforms. Although different implementations differ in the way they merge the conceptually different computational models, they all follow similar principles: they harness the parallelism and data synchronization inherent to the dataflow model, yet maintain the programmability of the von-Neumann model. In this paper, we classify hybrid dataflow/von-Neumann models according to two different taxonomies: one based on the execution model used for inter- and intrablock execution, and the other based on the integration level of both control and dataflow execution models. The paper reviews the basic concepts of von-Neumann and dataflow computing models, highlights their inherent advantages and limitations, and motivates the exploration of a synergistic hybrid computing model. Finally, we compare a representative set of recent general purpose hybrid dataflow/von-Neumann architectures, discuss their different approaches, and explore the evolution of these hybrid processors.