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Ahmet Ceyhan

dblp:130/7616 · DBLP profile ↗
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3ranked-venue papers
0as first author
1since 2021 · last 2026
0009-0001-8070-431XORCID · corroborated

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 3 · 1 since 2021Applied, interdisciplinary, general and emerging computing · 1

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Integrated circuit design · 44% Interconnection networks and networks-on-chip · 44% Emerging computing paradigms · 13%

Topics — the 3 heaviest of 3, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Interconnection networks and networks-on-chip › interconnect architecture
emerging interconnect
0.212014
BEOL Scaling Limits and Next Generation Technology Prospects · DAC 2014
Integrated circuit design
interconnect
0.212014
BEOL Scaling Limits and Next Generation Technology Prospects · DAC 2014
Emerging computing paradigms › spintronics › spintronic computing
all-spin logic
0.112014
BEOL Scaling Limits and Next Generation Technology Prospects · DAC 2014

Methods — techniques the papers use, named apart from their topics

technology scaling analysis · 0.2
YearPublicationVenuePosition
2026 GT2N: An Open-Source 2nm Nanosheet PDK Enabling Multi-Width/VT Benchmarking
Dongwon Jang, Md. Nahid Haque Shazon, Sabareesh Jeevan Ram, Alexei Svizhenko, Victor Moroz, Ahmet Ceyhan, Nischal Arkali Radhakrishna, Azad Naeemi
ISCAS7
2014 BEOL Scaling Limits and Next Generation Technology Prospects
abstract
This paper presents the major limitations to the interconnect technology scaling at future technology generations and demonstrates both evolutionary and radical potential solutions to the BEOL scaling problem. To address the local interconnect challenges, a novel hybrid Al-Cu interconnect technology is introduced. Performances of carbon-based interconnects are evaluated as a more radical solution. The impact of interconnects and the optimal interconnect options are investigated for emerging next generation devices. Interconnects for new state variables, namely spintronic interconnects, are studied and their potential performances in an all-spin logic system are evaluated.
Azad Naeemi, Ahmet Ceyhan, Vachan Kumar, Chenyun Pan, Rouhollah Mousavi Iraei, Shaloo Rakheja
DAC2
2014 Performance modeling for emerging interconnect technologies in CMOS and beyond-CMOS circuits
abstract
In this paper, emerging low-power interconnect options for CMOS and beyond CMOS technologies are reviewed. First, electrical interconnects based on carbon nanotubes and graphene nanoribbons are discussed. It is found that carbon-based electrical interconnects can potentially outperform their conventional Cu counterpart at technology nodes close to or below 10 nm. Next, since using electron spin as a novel state variable has attracted major attention, interconnect options for beyond-COMS spintronic devices will be discussed. We start with metallic interconnects based on the non-local spin-valve and spin-torque-driven switching, and the impact of size effects and dimensional scaling on their potential performance is studied. It is found that the spin signal in the non-local structure decays significantly because of a large degradation in the spin relaxation length as the interconnect width decreases. Next, a spintronic interconnect in the form of a conventional spin-valve configuration is introduced to increase the energy efficiency by eliminating the loss of spins in the non-local structure. Both metallic and semiconducting channels are studied, and the results show that the metallic interconnect is more energy-efficient than the semiconducting one when the interconnect is short (a few hundreds of nanometers) due to a high conductive current path. However, a semiconducting channel is appropriate for an intermediate or long (several microns) interconnect due to a longer spin relaxation time and the possibility of using an electric field to enhance the spin relaxation length. Furthermore, it is shown that for spin interconnects, downscaling the size of the ferromagnets can largely reduce the delay, energy, and energy-delay product at the cost of a shorter retention time.
Sou-Chi Chang, Ahmet Ceyhan, Vachan Kumar, Azad Naeemi
ISLPED2