Demonstration venue · read-only. Every page can be browsed; the buttons that would change it are switched off. Create an account to run TaxoReview on your own data. A simulation from public publication records: the people listed were not invited and did not agree to review.
? Tutorial for this page

Adam N. Jacobvitz

dblp:130/7750 · DBLP profile ↗
← Back
2ranked-venue papers
2as first author
0since 2021 · last 2015
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 1 · 1 first-authorSoftware engineering, systems software and programming languages · 1 · 1 first-author

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Memory systems · 61% Hardware reliability and fault tolerance · 39%
Theoretical computer science
1 paper
Coding theory · 100%

Topics — the 5 heaviest of 5, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Hardware reliability and fault tolerance › reliability analysis
lifetime reliability
0.212013
Coset coding to extend the lifetime of memory · HPCA 2013
Memory systems
non-volatile memory
0.212013
Coset coding to extend the lifetime of memory · HPCA 2013
Memory systems › non-volatile memory
phase change memory
0.212013
Coset coding to extend the lifetime of memory · HPCA 2013
Coding theory › error-correcting codes › code construction
coset coding
0.212013
Coset coding to extend the lifetime of memory · HPCA 2013
Hardware reliability and fault tolerance
soft errors
0.012013
Coset coding to extend the lifetime of memory · HPCA 2013

Methods — techniques the papers use, named apart from their topics

flipmin · 0.3
YearPublicationVenuePosition
2015 Multi-program benchmark definition
abstract
Although definition of single-program benchmarks is relatively straight-forward-a benchmark is a program plus a specific input-definition of multi-program benchmarks is more complex. Each program may have a different runtime and they may have different interactions depending on how they align with each other. While prior work has focused on sampling multiprogram benchmarks, little attention has been paid to defining the benchmarks in their entirety. In this work, we propose a four-tuple that formally defines multi-program benchmarks in a well-defined way. We then examine how four different classes of benchmarks created by varying the elements of this tuple align with real-world use-cases. We evaluate the impact of these variations on real hardware, and see drastic variations in results between different benchmarks constructed from the same programs. Notable differences include significant speedups versus slowdowns (e.g., +57% vs -5% or +26% vs -18%), and large differences in magnitude even when the results are in the same direction (e.g., 67% versus 11%).
Adam N. Jacobvitz, Andrew D. Hilton, Daniel J. Sorin
ISPASS1
2013 Coset coding to extend the lifetime of memory
abstract
Some recent memory technologies, including phase change memory (PCM), have lifetime reliabilities that are affected by write operations. We propose the use of coset coding to extend the lifetimes of these memories. The key idea of coset coding is that it performs a one-to-many mapping from each dataword to a coset of vectors, and having multiple possible vectors provides the flexibility to choose the vector to write that optimizes lifetime. Our technique, FlipMin, uses coset coding and, for each write, selects the vector that minimizes the number of bits that must flip. We also show how FlipMin can be synergistically combined with the ability to tolerate bit erasures. Thus, our techniques help to prevent bits from wearing out and can then tolerate those bits that do wear out.
Adam N. Jacobvitz, A. Robert Calderbank, Daniel J. Sorin
HPCA1