Demo Data from EDBT 2026 / reviewers in the wild / expert
Jacob Brock
dblp:130/7805
· DBLP profile ↗
11ranked-venue papers
4as first author
0since 2021 · last 2018
—ORCID · none
Domains — the database's venue-derived domains; a paper can count in several
Software engineering, systems software and programming languages · 6 · 3 first-authorSystems, architecture and hardware · 5 · 1 first-author
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
2 papers |
Memory systems · 43% Parallel and multicore computing · 29% GPUs and heterogeneous computing · 14% | |
| Software engineering, system software, and programming languages
1 paper |
Runtime systems and virtual machines · 100% |
Topics — the 8 heaviest of 9, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Runtime systems and virtual machines › dynamic compilation
just-in-time compilation |
0.3 | 1 | 2018 | ShareJIT: JIT code cache sharing across processes and its practical implementation · Proc. ACM Program. Lang. 2018 |
Memory systems
cache management |
0.3 | 1 | 2017 | Cache Exclusivity and Sharing: Theory and Optimization · ACM Trans. Archit. Code Optim. 2017 |
Performance modeling and evaluation
cache performance modeling |
0.3 | 1 | 2017 | Cache Exclusivity and Sharing: Theory and Optimization · ACM Trans. Archit. Code Optim. 2017 |
Memory systems › cache management
cache sharing |
0.3 | 1 | 2017 | Cache Exclusivity and Sharing: Theory and Optimization · ACM Trans. Archit. Code Optim. 2017 |
Parallel and multicore computing › concurrent programming
concurrency bugs |
0.3 | 1 | 2017 | LD: Low-Overhead GPU Race Detection Without Access Monitoring · ACM Trans. Archit. Code Optim. 2017 |
Parallel and multicore computing › parallel computing › parallel program debugging
data race detection |
0.3 | 1 | 2017 | LD: Low-Overhead GPU Race Detection Without Access Monitoring · ACM Trans. Archit. Code Optim. 2017 |
Memory systems › memory hierarchy › cache hierarchy management
exclusive caching |
0.3 | 1 | 2017 | Cache Exclusivity and Sharing: Theory and Optimization · ACM Trans. Archit. Code Optim. 2017 |
GPUs and heterogeneous computing
GPU programming |
0.3 | 1 | 2017 | LD: Low-Overhead GPU Race Detection Without Access Monitoring · ACM Trans. Archit. Code Optim. 2017 |
Methods — techniques the papers use, named apart from their topics
profiling data sharing · 0.3optimization restriction for shareability · 0.3value-based checking · 0.3hardware counter measurement · 0.3compiler instrumentation · 0.3analytical performance modeling · 0.3
| Year | Publication | Venue | Position |
|---|---|---|---|
| 2018 | PAYJIT: space-optimal JIT compilation and its practical implementationabstractJust-in-time (JIT) compilation in dynamic programming languages can improve execution speed in code with hot sections. However, that comes at the cost of increased memory usage for the storage of compiled code and associated bookkeeping data, as well as up-front compilation time for the hot code. Jacob Brock, Chen Ding 0001 |
CC | 1 |
| 2018 | Prediction and bounds on shared cache demand from memory access interleavingabstractCache in multicore machines is often shared, and the cache performance depends on how memory accesses belonging to different programs interleave with one another. The full range of performance possibilities includes all possible interleavings, which are too numerous to be studied by experiments for any mix of non-trivial programs. Jacob Brock, Chen Ding 0001, Rahman Lavaee, Fangzhou Liu 0004 |
ISMM | 1 |
| 2018 | ShareJIT: JIT code cache sharing across processes and its practical implementationabstractJust-in-time (JIT) compilation coupled with code caching are widely used to improve performance in dynamic programming language implementations. These code caches, along with the associated profiling data for the hot code, however, consume significant amounts of memory. Furthermore, they incur extra JIT compilation time for their creation. On Android, the current standard JIT compiler and its code caches are not shared among processes—that is, the runtime system maintains a private code cache, and its associated data, for each runtime process. However, applications running on the same platform tend to share multiple libraries in common. Sharing cached code across multiple applications and multiple processes can lead to a reduction in memory use. It can directly reduce compile time. It can also reduce the cumulative amount of time spent interpreting code. All three of these effects can improve actual runtime performance. In this paper, we describe ShareJIT, a global code cache for JITs that can share code across multiple applications and multiple processes. We implemented ShareJIT in the context of the Android Runtime (ART), a widely used, state-of-the-art system. To increase sharing, our implementation constrains the amount of context that the JIT compiler can use to optimize the code. This exposes a fundamental tradeoff: increased specialization to a single process’ context decreases the extent to which the compiled code can be shared. In ShareJIT, we limit some optimization to increase shareability. To evaluate the ShareJIT, we tested 8 popular Android apps in a total of 30 experiments. ShareJIT improved overall performance by 9% on average, while decreasing memory consumption by 16% on average and JIT compilation time by 37% on average. Keith D. Cooper, Jacob Brock, Handong Ye |
Proc. ACM Program. Lang. | 3 |
| 2017 | LD: Low-Overhead GPU Race Detection Without Access MonitoringabstractData race detection has become an important problem in GPU programming. Previous designs of CPU race-checking tools are mainly task parallel and incur high overhead on GPUs due to access instrumentation, especially when monitoring many thousands of threads routinely used by GPU programs. This article presents a novel data-parallel solution designed and optimized for the GPU architecture. It includes compiler support and a set of runtime techniques. It uses value-based checking, which detects the races reported in previous work, finds new races, and supports race-free deterministic GPU execution. More important, race checking is massively data parallel and does not introduce divergent branching or atomic synchronization. Its slowdown is less than 5 × for over half of the tests and 10 × on average, which is orders of magnitude more efficient than the cuda-memcheck tool by Nvidia and the methods that use fine-grained access instrumentation. Pengcheng Li 0001, Dong Chen 0015, Jacob Brock, Hao Luo 0007, Eddy Z. Zhang, Chen Ding 0001 |
ACM Trans. Archit. Code Optim. | 4 |
| 2017 | Cache Exclusivity and Sharing: Theory and OptimizationabstractA problem on multicore systems is cache sharing, where the cache occupancy of a program depends on the cache usage of peer programs. Exclusive cache hierarchy as used on AMD processors is an effective solution to allow processor cores to have a large private cache while still benefitting from shared cache. The shared cache stores the “victims” (i.e., data evicted from private caches). The performance depends on how victims of co-run programs interact in shared cache. This article presents a new metric called the victim footprint (VFP). It is measured once per program in its solo execution and can then be combined to compute the performance of any exclusive cache hierarchy, replacing parallel testing with theoretical analysis. The work evaluates the VFP by using it to analyze cache sharing by parallel mixes of sequential programs, comparing the accuracy of the theory to hardware counter results, and measuring the benefit of exclusivity-aware analysis and optimization. Chencheng Ye 0001, Chen Ding 0001, Hao Luo 0007, Jacob Brock, Dong Chen 0015, Hai Jin 0001 |
ACM Trans. Archit. Code Optim. | 4 |
| 2016 | Compositional model of coherence and NUMA effects for optimizing thread and data placementabstractOn today's multi-socket systems, the parallel performance is hampered by remote cache and memory access. There is much prior work on thread and data placement to curb remote access. However, the number of possible placements is large, and heuristic-based techniques only examines a fraction of the entire solution space. This paper presents a compositional model to analyze the effect of thread and data placement choices. The model includes an analysis for cache coherence and (remote) memory access. It has the property of being compositional, meaning the performances of all the placements can be composed from the results of one profiling pass. Based on this model, this paper further introduces a prototype tool called Tapas to optimize parallel programs for non-uniform memory access (NUMA) platforms. Hao Luo 0007, Jacob Brock, Pengcheng Li 0001, Chen Ding 0001, Chencheng Ye 0001 |
ISPASS | 2 |
| 2016 | Hardware support for protective and collaborative cache sharingabstractShared caches are generally optimized to maximize the overall throughput, fairness, or both, among multiple competing programs. In shared environments and compute clouds, users are often unrelated to each other. In such circumstances, an overall gain in throughput does not justify an individual loss. This paper explores cache management policies that allow conservative sharing to protect the cache occupancy for individual programs, yet enable full cache utilization whenever there is an opportunity to do so. We propose a hardware-based mechanism called cache rationing. Each program is assigned a portion of the shared cache as its ration. The hardware support protects the ration so it cannot be taken away by peer programs while in use. However, a program can exceed its pre-allocated ration, but only if another program has unused space in its allocated portion of ration. We show that rationing provides good resource protection and full cache utilization of the shared cache for a variety of co-runs. Raj Parihar, Jacob Brock, Chen Ding 0001, Michael C. Huang 0001 |
ISMM | 2 |
| 2015 | Optimal Footprint Symbiosis in Shared CacheabstractOn multicore processors, applications are run sharing the cache. This paper presents online optimization to collocate applications to minimize cache interference to maximize performance. The paper formulates the optimization problem and solution, presents a new sampling technique for locality analysis and evaluates it in an exhaustive test of 12,870 cases. For locality analysis, previous sampling was two orders of magnitude faster than full-trace analysis. The new sampling reduces the cost by another two orders of magnitude. The best prior work improves co-run performance by 56% on average. The new optimization improves it by another 29%. When sampling and optimization are combined, the paper shows that it takes less than 0.1 second analysis per program to obtain a co-run that is within 1.5% of the best possible performance. Xiaolin Wang 0001, Yechen Li, Yingwei Luo, Xiameng Hu, Jacob Brock, Chen Ding 0001, Zhenlin Wang 0003 |
CCGRID | 5 |
| 2015 | Optimal Cache Partition-SharingabstractWhen a cache is shared by multiple cores, its space may be allocated either by sharing, partitioning, or both. We call the last case partition-sharing. This paper studies partition-sharing as a general solution, and presents a theory an technique for optimizing partition-sharing. We present a theory and a technique to optimize partition sharing. The theory shows that the problem of partition-sharing is reducible to the problem of partitioning. The technique uses dynamic programming to optimize partitioning for overall miss ratio, and for two different kinds of fairness. Finally, the paper evaluates the effect of optimal cache sharing and compares it with conventional solutions for thousands of 4-program co-run groups, with nearly 180 million different ways to share the cache by each co-run group. Optimal partition-sharing is on average 26% better than free-for-all sharing, and 98% better than equal partitioning. We also demonstrate the trade-off between optimal partitioning and fair partitioning. Jacob Brock, Chencheng Ye 0001, Chen Ding 0001, Yechen Li, Xiaolin Wang 0001, Yingwei Luo |
ICPP | 1 |
| 2014 | Protection and utilization in shared cache through rationingabstractShared cache is generally optimized for overall throughput, fairness, or both. Increasingly in shared environments, e.g., compute clouds, users are unrelated to one another. In such circumstances, an overall gain in throughput does not justify an individual loss. This paper explores a new strategy for conservative sharing, which protects the cache occupancy for individual programs, but still enables full cache sharing whenever there is unused space. Raj Parihar, Jacob Brock, Chen Ding 0001, Michael C. Huang 0001 |
PACT | 2 |
| 2013 | Pacman: program-assisted cache managementabstractAs caches become larger and shared by an increasing number of cores, cache management is becoming more important. This paper explores collaborative caching, which uses software hints to influence hardware caching. Recent studies have shown that such collaboration between software and hardware can theoretically achieve optimal cache replacement on LRU-like cache. Jacob Brock, Xiaoming Gu, Bin Bao, Chen Ding 0001 |
ISMM | 1 |