Long Term Evolution (LTE) communications systems are increasingly being used for remote applications where a battery life of 10 to 15 years can be specified. To ensure these demands can be met, accurate modelling of power consumption is required. Existing models which decompose LTE power consumption focus on laboratory-only measurements and use continuous transmission scenarios. The work presented shows that whilst these are valid for the continuous case, they are not relevant for Machine to Machine (M2M) activity on a live network. Under these conditions, packet size is likely to be small in relation to protocol and system overheads, resulting in a dramatically increased and hard to model consumption of power. In addition, network measurement and optimisation transmissions in supposedly low power idle periods threaten to further confound the issue.

This invited paper considers a key next step in the design of radio architectures aimed at supporting low energy consumption in 5G heterogeneous radio access networks. State-of-the-art mobile radios usually require one RF transceiver per standard, each working separately at any given time. Software defined radios, while spanning a wide range of standards and frequency bands, also work separately at any specific time. In 5G radio access networks, where continuous, multiband connectivity is envisaged, this conventional radio architecture results in high network power consumption. In this paper, we propose the novel concept of a concurrent multiband frequency-agile radio (CM-FARAD) architecture, which simultaneously supports multiple standards and frequency bands using a single, tunable transceiver. We discuss the subsystem radio design approaches for enabling the CM-FARAD architecture, including antennas, power amplifiers, low noise amplifiers and analogue to digital converters. A working prototype of a dual-band CM-FARAD test-bed is also presented together with measured salient performance characteristics.

In-Band Full Duplex (IBFD) transceivers can potentially provide significant increases in spectral efficiency by allowing simultaneous transmit and receive on the same frequency at the same time. However any such gains are conditional on effective cancellation of the self-interference. The performance of a self-interference cancellation transceiver depends not only on the system design, but also on implementation specific parameters of the transceiver and cancellation circuitry. Thus, realistic evaluation of cancellation performance can only be performed using hardware prototypes. This paper provides a detailed overview of a highly flexible and reconfigurable self-interference cancellation testbed, which combines active cancellation with either separate Tx and Rx antennas, or an Electrical Balance Duplexer, along with digital baseband cancellation. The system can facilitate investigation on self-interference cancellation performance across a range of physical layer configurations, and provide a platform for the rapid prototyping of digital baseband algorithms within an operational self-interference cancelling transceiver.

Electrical balance duplexers can provide high transmit-to-receive isolation whilst facilitating transmission and reception from a single antenna, can be implemented on-chip, and are widely tunable, making this an attractive technology for implementing full duplex architectures in small form factor devices. This paper presents measurements from a novel hardware prototype full-duplex transceiver architecture combining electrical balance and active analog cancellation. The prototype duplexer achieves >80dB transmit-to-receive isolation over a 20MHz bandwidth at both 890MHz and 1890MHz, exceeding the performance of antenna separation architectures where the antenna isolation is limited to the levels achievable in hand held devices.

A key issue impacting the transmit to receive (TX-RX) isolation in Electrical Balance (EB) Duplexers is dynamic matching of the antenna impedance by the balancing network. Circuit simulations including embedded antenna measurements have been used to investigate the variation in TX-RX isolation due to interaction with the user and the local environment. Simulated results at 847MHz and 1960MHz show user interaction causes over 25dB of variation in the mean isolation over a 20MHz bandwidth. However, in reflective indoor environments, user interaction on average improves TX-RX isolation. This observed performance improvement is a result of reduced antenna radiation efficiency, which makes reflections from objects at longer ranges less significant and thereby reduces frequency domain variation in the antenna reflection coefficient.

This paper investigates electrical balance (EB) in hybrid junctions as a method of achieving transmitter-receiver isolation in single antenna full duplex wireless systems. A novel technique for maximizing isolation in EB duplexers is presented, and we show that the maximum achievable isolation is proportional to the variance of the antenna reflection coefficient with respect to frequency. Consequently, antenna characteristics can have a significant detrimental impact on the isolation bandwidth. Simulations that include embedded antenna measurements show a mean isolation of 62 dB over a 20-MHz bandwidth at 1.9 GHz but relatively poor performance at wider bandwidths. Furthermore, the operational environment can have a significant impact on isolation performance. We present a novel method of characterizing radio reflections being returned to a single antenna. Results show as little as 39 dB of attenuation in the radio echo for a highly reflective indoor environment at 1.9 GHz and that the mean isolation of an EB duplexer is reduced by 7 dB in this environment. A full duplex architecture exploiting EB is proposed.

Sequential decoding can achieve high throughput convolutional decoding with much lower computational complexity when compared with the Viterbi algorithm (VA) at a relatively high signal-to-noise ratio (SNR). A parallel bidirectional Fano algorithm (BFA) decoding architecture is investigated in this paper. In order to increase the utilisation of the parallel BFA decoders, and thus improve the decoding throughput, a state estimation method is proposed which can effectively partition a long codeword into multiple short sub-codewords. The parallel BFA decoding with state estimation architecture is shown to achieve 30–55% decoding throughput improvement compared with the parallel BFA decoding scheme without state estimation. Compared with the VA, the parallel BFA decoding only requires 3–30% computational complexity of that required by the VA with a similar error rate performance.

In this paper, a bidirectional Fano algorithm (BFA) is proposed, in which a forward decoder (FD) and a backward decoder (BD) search in the opposite direction in the code tree simultaneously. It is shown that the proposed BFA can achieve more than twice the decoding throughput compared to the conventional unidirectional Fano algorithm (UFA) and there is higher throughput improvement at low signal-to-noise ratio (SNR). This new BFA decoding technique is applied in the parallel convolutional decoding architecture in very high throughput systems, such as the WirelessHD system. Due to the variability in the decoding delays of the parallel codewords, a scheduler is introduced in the parallel Fano decoding architecture which can dynamically allocate the idle decoders to assist with decoding the other parallel codewords in a bidirectional manner. It is shown that the proposed parallel Fano decoding with scheduling can dramatically increase the decoding throughput compared to the parallel Fano decoding without scheduling, and its computational complexity is much lower than that of parallel Viterbi decoding, especially at high SNR. The performance of the parallel Fano decoding with different scheduling schemes is also compared and analyzed in detail in the paper.

The bidirectional Fano algorithm (BFA) can achieve at least two times decoding throughput compared to the conventional unidirectional Fano algorithm (UFA). In this paper, bidirectional Fano decoding is examined from the queuing theory perspective. A Discrete Time Markov Chain (DTMC) is employed to model the BFA decoder with a finite input buffer. The relationship between the input data rate, the input buffer size and the clock speed of the BFA decoder is established. The DTMC based modelling can be used in designing a high throughput parallel BFA decoding system. It is shown that there is a trade-off between the number of BFA decoders and the input buffer size, and an optimal input buffer size can be chosen to minimize the hardware complexity for a target decoding throughput in designing a high throughput parallel BFA decoding system.

Recently, we introduced a bidirectional Fano algorithm (BFA) [10] which can achieve much higher decoding throughput compared to the regular unidirectional Fano algorithm (UFA), especially at low signal-to-noise-ratio (SNR). However, the decoding throughput improvement of the conventional BFA with respect to the UFA reduces as the SNR increases and converges to 100% at high SNR. In this paper, two parameters in the BFA, which are known as the number of merged states (NMS) and the threshold increment value Δ, are exploited to improve the decoding throughout of the conventional BFA. The improved BFA can achieve much higher decoding throughput compared to the UFA and the conventional BFA, especially at high SNR. For example at Eb/N0=5dB, the throughput improvement achieved by the improved BFA is about 280% compared to the UFA and about 80% compared to the conventional BFA, and its computational complexity is only 4% of the Viterbi algorithm.

Various techniques, such as bidirectional search, have been employed in sequential decoding to reduce the decoding delay. In this paper, a bidirectional Fano algorithm (BFA) is proposed, in which a forward decoder (FD) and a backward decoder (BD) search in the opposite direction simultaneously. It is shown that the proposed BFA can reduce the average decoding delay by at least 50% compared to the unidirectional Fano algorithm (UFA). Due to the reduction in the variability of the computational effort by using bidirectional search, there is even higher decoding throughput improvement at low signal-to-noise-ratio (SNR). For example at Eb/No=3dB, there is 300% throughput improvement by using the BFA decoding compared to the conventional UFA decoding. The proposed BFA decoding technique can be employed in very high throughput wireless communication systems with low hardware complexity and power consumption.

The inefficiency of contemporary power amplifiers (PAs), when operating in their linear region, is a major obstacle to mobile operation of wireless local area networks (WLANs) based on IEEE 802.11n. Therefore the use of more efficient envelope elimination and restoration (EER) transmitter architectures is considered. In addition to high efficiency it is also necessary to satisfy the spectral mask and achieve satisfactory link-level performance. Link-level simulations of a contemporary WLAN PA show that, at the power back-offs necessary to achieve sufficient linearity, the power added efficiency (PAE) is only ∼1% for a system with four transmit antennas. In contrast, simulations of a phase feedback EER PA architecture show that it is possible to achieve an average PAE of 70%, while satisfying the spectral mask, with only a small degradation in link-level performance.