Learning math is important for the academic life of students: the development of mathematical skills is influenced by different characteristics of students such as geographical position, economic level, parents’ education, achievement level, teacher objectives, social level, use of information and communication technologies by teachers, learner motivation, gender, age, preferences for playing video games, and the school year of the students. In this work, these previously mentioned characteristics were considered as the attributes (inputs) of a multilayer neural network that uses a backpropagation algorithm to predict the percentage of improvement in mathematics through a 2D mathematical video game that was developed to allow the children to practice addition and subtraction operations. After applying the neural model, using the twelve attributes mentioned before and the backpropagation algorithm, there was a network of one layer with ten neurons and another network of two layers with 5 neurons in the first layer and 20 neurons in the second layer. Both architectures produced a mean squared error smaller than 0.0069 in the prediction of the student’s percentage of improvement in mathematics, being the best configurations found in this study for the neural model. These results lead to the conclusion that we are able to predict the percentage of improvement in math that the students could achieve after playing the game, and therefore, claiming if the video game is recommendable or not for certain students.

The well-known backpropagation learning algorithm is implemented in a field-programmable gate array (FPGA) board and a microcontroller, focusing in obtaining efficient implementations in terms of a resource usage and computational speed. The algorithm was implemented in both cases using a training/validation/testing scheme in order to avoid overfitting problems. For the case of the FPGA implementation, a new neuron representation that reduces drastically the resource usage was introduced by combining the input and first hidden layer units in a single module. Further, a time-division multiplexing scheme was implemented for carrying out product computations taking advantage of the built-in digital signal processor cores. In both implementations, the floating-point data type representation normally used in a personal computer (PC) has been changed to a more efficient one based on a fixed-point scheme, reducing system memory variable usage and leading to an increase in computation speed. The results show that the modifications proposed produced a clear increase in computation speed in comparison with the standard PC-based implementation, demonstrating the usefulness of the intrinsic parallelism of FPGAs in neurocomputational tasks and the suitability of both implementations of the algorithm for its application to the real world problems.

A two-dimensional Ising model with nearest-neighbors ferromagnetic interactions is implemented in a Field Programmable Gate Array (FPGA) board. Extensive Monte Carlo simulations were carried out using an efficient hardware representation of individual spins and a combined global-local LFSR random number generator. Consistent results regarding the descriptive properties of magnetic systems, like energy, magnetization and susceptibility are obtained while a speed-up factor of approximately six times is achieved in comparison to previous FPGA-based published works and almost$10^4$times in comparison to a standard CPU simulation. A detailed description of the logic design used is given together with a careful analysis of the quality of the random number generator used. The obtained results confirm the potential of FPGAs for analyzing the statistical mechanics of magnetic systems.

Competitive majority network trained by error correction (C-Mantec), a recently proposed constructive neural network algorithm that generates very compact architectures with good generalization capabilities, is implemented in a field programmable gate array (FPGA). A clear difference with most of the existing neural network implementations (most of them based on the use of the backpropagation algorithm) is that the C-Mantec automatically generates an adequate neural architecture while the training of the data is performed. All the steps involved in the implementation, including the on-chip learning phase, are fully described and a deep analysis of the results is carried on using the two sets of benchmark problems. The results show a clear increase in the computation speed in comparison to the standard personal computer (PC)-based implementation, demonstrating the usefulness of the intrinsic parallelism of FPGAs in the neurocomputational tasks and the suitability of the hardware version of the C-Mantec algorithm for its application to real-world problems.