Dynamic logic is a high-speed technology that was previously used in mature technologies, but lost popularity due to the increased leakage and process variations in advanced technologies. However, the recent popularity of circuits running in the cryogenic region provides a new opportunity for dynamic operation, thanks to the reduced leakages at such low temperatures. This paper revisits dynamic logic as a true candidate for high-performance and energy-efficient circuits for cryogenic operation in nanoscaled technologies. The paper first overviews and analyzes transistor operation at cryogenic temperatures and how it influences digital circuit design targeted to this regime. With these effects in mind, the use of dynamic logic families, including the classical dynamic (NORA) logic and the recently introduced Dual Mode Logic (DML) and Dual Mode Pass Logic (DMPL) families, are examined under cryogenic operation, showcasing improved performance and power efficiency. Measurements conducted on a 16 nm FinFET test chip validate their operation at low temperatures down to 4K, with supply voltages ranging 0.4–0.8-V. Furthermore, the considered dual mode logic families exhibit performance enhancements of up to 26% in dynamic mode and power efficiency increases up to 53% in static mode, compared to CMOS.

Electromagnetic (EM) side channel analysis (SCA) attacks have evolved to a significant threat for integrated circuits (ICs). Radiation, emanated from devices which manipulate sensitive information, carries it with a sufficient signal-to-noise ratio. Security evaluation in design stages, from a model or from a simulation, is complicated and hard to argue for correctness. Extensive literature exist on attacks utilizing EM signals. However, both frontiers of simulatability and modeling of the radiation have shown rather little research effort in the past in the SCA context. On simulatability prior work investigated utilization of complete EM physical solvers, such as COMSOL, HFSS which require much effort from the user/engineer to model the electronic environment, or alternatively used simulated (SPICE) currents within IC’s design kits and from it provide analytical estimation. On the modeling side, efforts were mainly limited to either: a specific EM component (e.g., magnetic), very limited scope of the model, or a limited connection with real-life IC. The main contributions of this research are: 1) providing a fully analytical model of the radiated signal considering the ground plane of the substrate and the medium change from oxidation layers to other mediums, such as air or plastic, utilizing EM theory-of-images for both E and H fields; 2) providing methodologies to simulate EM signals on IC-technologies (by adapting Cadence EMX tool); and 3) demonstrating little error between the analytical and simulated models and linking cryptographic SCA security metrics to the analytical tools. The developed model provides significant added value for security architects, faster, premanufacturing evaluation and a verifiability framework through IC tool.

This work proposes a novel platform for bringing a project from the concept to the tapeout stage in a short amount of time. An open-source and extendable RISC-V architecture is exploited to build a small area footprint core. This leads the research platform to be flexible in terms of design integration, while also allowing fast design cycles of research chips.

Dual Mode Logic (DML) enables the dynamical operation of digital circuits optimized for energy-delay efficiency. Here, for the first time, DML is examined under cryogenic conditions, and its characteristics are evaluated for future applications. As a proof-of-concept, a DML testchip designed in 65nm technology was measured under cryogenic temperatures down to 4K. Measurements at supply voltages from 0.8V to 1.2V and temperatures ranging from 300K (room temperature) to 4K, confirm the effectiveness of DML under extreme temperatures.

Compact protection codes (CPCs) provide optimal protection against fault injections attacks on memory arrays content. Nevertheless, CPCs fail to detect errors injected into the address itself. Consequently, an adversary can write a correct data word to an erroneous address without being detected. This paper presents an efficient code, dubbed AD-CPC, which detects both data manipulations and faults injected into the address decoder. No additional redundancy bits are required and no latency is introduced. In addition, the new encoding has a negligible effect on the error masking probability of the original CPC. We provide theoretical bounds and experimental results that support these claims. We show that with r additional redundant bits every error can be detected with probability of at least 1 - 3.2-r.

Side channel analysis attacks are considered an extreme hardware security hazard for cryptographic devices. There are numerous approaches to prevent attackers from extracting useful information from secured devices. Nonetheless the cost of implementing an effective countermeasure is usually very high in terms of area/performance. In this paper we propose a novel approach to the temporal redistribution of the power information. Specifically, we present a circuit level methodology that makes it possible to manipulate the three main parameters of the current profile during the clock period: the start time of the computation, the duration and the amplitude. The effectiveness of the proposed countermeasure was evaluated on a 4-bit cryptographic function in a 65nm TSMC process. The simulation results indicate that the number of secret bits that leaked from the protected design (i.e., the mutual information) was reduced dramatically from 4 bits to 0.85 bits. In addition, at least 1500 ideal noise-free power traces were required to extract these bits, whereas less than 150 traces were required to extract the whole 4 bits from the unprotected design. The sensitivity of the protected circuit to process and environmental variations are minimal, with measured standard deviation of 0.1bit. The area overhead is up to 32%.

An SRAM Physical Unclonable Function (PUF) cell is fabricated and reported, which has two bits per cell. The Decision Voltage of the cell is analyzed and the cell is designed such that only the NMOS devices in the latch configuration contribute to the cell response. Either one of two pairs of NMOS devices is selected, such that two independent bits are generated. The cell was fabricated and measured in TSMC 65nm technology with a highly competitive area of 1420F2per bit.