Maxwell Hutchinson

dblp:131/6746 · DBLP profile ↗
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3ranked-venue papers
1as first author
0since 2021 · last 2020
0000-0002-7425-4156ORCID · corroborated

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 2Theory of computation · 1 · 1 first-author

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Software engineering, system software, and programming languages
1 paper
Runtime systems and virtual machines · 100%
Computer architecture, parallel and distributed computing, and storage systems
1 paper
High-performance computing · 62% Processor architecture and microarchitecture · 38%

Topics — the 5 heaviest of 5, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Runtime systems and virtual machines › dynamic compilation
just-in-time compilation
0.212016
LIBXSMM: accelerating small matrix multiplications by runtime code generation · SC 2016
Runtime systems and virtual machines › dynamic compilation
run-time code generation
0.212016
LIBXSMM: accelerating small matrix multiplications by runtime code generation · SC 2016
High-performance computing
performance optimization at scale
0.212016
LIBXSMM: accelerating small matrix multiplications by runtime code generation · SC 2016
Processor architecture and microarchitecture › instruction set architecture
instruction set extension
0.112016
LIBXSMM: accelerating small matrix multiplications by runtime code generation · SC 2016
Processor architecture and microarchitecture › SIMD
vector instructions
0.112016
LIBXSMM: accelerating small matrix multiplications by runtime code generation · SC 2016

Methods — techniques the papers use, named apart from their topics

code generation · 0.5cache hierarchy · 0.5auto-tuning · 0.5
YearPublicationVenuePosition
2020 Performance study of sustained petascale direct numerical simulation on Cray XC40 systems
abstract
Summary We present in this paper a comprehensive performance study of highly efficient extreme scale direct numerical simulations of secondary flows, using an optimized version of Nek5000. Our investigations are conducted on various Cray XC40 systems, using a very high‐order spectral element method. Single‐node efficiency is achieved by auto‐generated assembly implementations of small matrix multiplies and key vector‐vector operations, streaming lossless I/O compression, aggressive loop merging, and selective single precision evaluations. Comparative studies across different Cray XC40 systems at scale, Trinity (LANL), Cori (NERSC), and ShaheenII (KAUST) show that a Cray programming environment, network configuration, parallel file system, and burst buffer all have a major impact on the performance. All three systems possess a similar hardware with similar CPU nodes and parallel file system, but they have different theoretical peak network bandwidths, different OSs, and different versions of the programming environment. Our study reveals how these slight configuration differences can be critical in terms of performance of the application. We also find that with 9216 nodes (294 912 cores) on Trinity XC40 the applications sustain petascale performance, as well as 50% of peak memory bandwidth over the entire solver (500 TB/s in aggregate). On 3072 Xeon Phi nodes of Cori, we reach 378 TFLOP/s with an aggregated bandwidth of 310 TB/s, corresponding to time‐to‐solution 2.11× faster than obtained with the same number of (dual‐socket) Xeon nodes.
Bilel Hadri, Matteo Parsani, Maxwell Hutchinson, Alexander Heinecke, Lisandro Dalcín, David E. Keyes
Concurr. Comput. Pract. Exp.3
2016 LIBXSMM: accelerating small matrix multiplications by runtime code generation
abstract
Many modern highly scalable scientific simulations packages rely on small matrix multiplications as their main computational engine. Math libraries or compilers are unlikely to provide the best possible kernel performance. To address this issue, we present a library which provides high performance small matrix multiplications targeting all recent x86 vector instruction set extensions up to Intel AVX-512. Our evaluation proves that speed-ups of more than 10× are possible depending on the CPU and application. These speed-ups are achieved by a combination of several novel technologies. We use a code generator which has a built-in architectural model to create code which runs well without requiring an auto-tuning phase. Since such code is very specialized we leverage just-in-time compilation to only build the required kernel variant at runtime. To keep ease-of-use, overhead, and kernel management under control we accompany our library with a BLAS-compliant frontend which features a multi-level code-cache hierarchy.
Alexander Heinecke, Greg Henry, Maxwell Hutchinson, Hans Pabst
SC3
2015 Enumeration of octagonal tilings
Maxwell Hutchinson, Michael Widom
Theor. Comput. Sci.1