Joint-Embedding Predictive Architectures (JEPAs), a powerful class of self-supervised models, exhibit an unexplained ability to cluster time-series data by their underlying dynamical regimes. We propose a novel theoretical explanation for this phenomenon, hypothesizing that JEPA's predictive objective implicitly drives it to learn the invariant subspace of the system's Koopman operator. We prove that an idealized JEPA loss is minimized when the encoder represents the system's regime indicator functions, which are Koopman eigenfunctions. This theory was validated on synthetic data with known dynamics, demonstrating that constraining the JEPA's linear predictor to be a near-identity operator is the key inductive bias that forces the encoder to learn these invariants. We further discuss that this constraint is critical for selecting this interpretable solution from a class of mathematically equivalent but entangled optima, revealing the predictor's role in representation disentanglement. This work demystifies a key behavior of JEPAs, provides a principled connection between modern self-supervised learning and dynamical systems theory, and informs the design of more robust and interpretable time-series models.

Today's industry is rapidly evolving towards Industry 4.0 in which the Internet of Things is transforming machines into highly-interactive cyber-physical systems. At its core, these cyber-physical systems are driven by industrial embedded systems. However, the trend of many interacting systems creates a harsher working environment for these embedded systems to operate in, considering among other things electromagnetic interference. This working environment can introduce bit flips in the embedded system's hardware which cause control flow and data flow errors in its control software. This paper analyzes the effects of such control flow errors on an Industry 4.0 setup. We also apply a software implemented control flow error detection method to determine its gain in reliability. Finally, this paper demonstrates a basic but effective automated recovery method for our Industry 4.0 setup.

Embedded systems used in harsh environments are susceptible to bit-flips, which can cause data flow errors. In order to increase the reliability of embedded systems, numerous data flow error detection techniques have already been developed. It is, however, difficult to identify the best technique to apply, due to differences in the way they are evaluated in current literature.

This paper presents a new software-implemented data error detection technique called Full Duplication and Selective Comparison. Our technique combines the ideas of existing techniques in order to increase the fault detection ratio, decrease the imposed code size and execution time overhead. As the name gives away, we opt to duplicate the entire code base and place comparison instructions in critical basic blocks only. The critical basic blocks are the blocks with two or more incoming edges. We evaluate our technique by implementing it for several case studies and by performing fault injection experiments. Next, we compared the obtained results to the parameters of three established techniques: Error Detection by Diverse Data and Duplicated Instructions, Critical Block Duplication and Software Implemented Fault Tolerance. The results show an average increase of 20.5% in fault detection ratio and an average decrease in code size and execution time overhead of 12.6% and 0.5%, respectively.