Physical dataflow, which defines the detailed connections among cells and macros, is a critical yet underexplored factor in automatic macro placement. It becomes increasingly important for enabling intelligent design automation to minimize manual intervention and reduce design iterations. Existing macro or mixed-size placers with dataflow awareness primarily focus on intrinsic relationships among macros, overlooking the crucial influence of standard cell clusters on macro placement. To address this, we propose DARE, which extracts hidden connections between macros and standard cells and incorporates a series of algorithms to enrich dataflow awareness, integrating them into placement constraints for improved macro placement. To further optimize placement results, we introduce two fine-tuning steps: (1) congestion optimization by taking macro area into consideration, and (2) flipping decisions to determine the optimal macro orientation based on the extracted dataflow information. By integrating enhanced dataflow awareness into placement constraints and applying these fine-tuning steps, the proposed approach achieves an average 7.9% improvement in half-perimeter wirelength (HPWL) across multiple widely used benchmark designs compared to a state-of-the-art dataflow-aware macro placer. Additionally, it significantly improves congestion, reducing overflow by an average of 82.5%, and achieves improvements of 36.97% in Worst Negative Slack (WNS) and 59.44% in Total Negative Slack (TNS). The approach also maintains efficient runtime throughout the entire placement, incurring less than a 1.5% runtime overhead. These results show that the proposed dataflow-driven methodology, combined with the fine-tuning steps, provides an effective foundation for macro placement within the OpenROAD flow and can be further extended to other design flows in the future to enhance placement quality.

Despite the maturity of Multi-bit Flip-Flops (MBFF) clustering in modern Electronic Design Automation (EDA) tools for saving power, there remains a trade-off between the flexibility to cluster flip-flops and the overall quality of results (QoR). This paper proposes a novel approach to MBFF clustering, integrating early-stage physical and timing awareness to optimize the design quality. Our pre-placement MBFF clustering algorithm addresses this trade-off by incorporating early distance estimation and predicted skews, improving timing conditions without compromising power savings. We evaluate our approach using widely-used benchmark circuits, demonstrating significant improvements in power savings and timing compared to state-of-the-art techniques. Notably, our method achieves an average improvement of 22.5% in Worst Negative Slack (WNS) and 33.91% in Total Negative Slack (TNS), while reducing power by 3.01% compared to commercial tools with MBFF clustering enabled at placement. Against the state-of-the-art pre-placement MBFF clustering algorithm, our methodology shows 25.59% and 37.97% improvements in WNS and TNS, respectively, while further reducing power by 3.08%. In addition, the proposed approach proves robust against variations in early-stage path delay estimation, maintaining superior performance even with deviations of over 20%.

In advanced technology nodes, the proliferation of process corners poses significant challenges in timing signoff, particularly in estimating wire-induced interconnect delay across process corners. This paper proposes a learning-based framework to perform cross-corner timing prediction efficiently and accurately. It seamlessly integrates learning-based reference corner selection and topology-aware interconnect timing prediction into the broader timing signoff steps and Engineering Change Order (ECO) processes. Unlike previous methods, it only requires information about one single known corner while accurately predicting all unknown corners. Evaluated on two mainstream industry processes, the proposed framework surpasses alternative machine learning models and existing strategies, with an impressive average accuracy enhancement of 62.6% and 95.3% respectively, and maintains a low mean absolute error (MAE) under 0.37ps and 0.01ps. Additionally, a faster version of the framework is developed to predict interconnect delay directly from a single extracted SPEF, yielding over 2× speedup. Moreover, the single-corner approach featured by the framework significantly accelerates ECO processes by over 10× compared to standard timing signoff flows. The proposed framework is also set to be open-sourced at a later date.