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Jens Axboe

dblp:132/0326 · DBLP profile ↗
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4ranked-venue papers
0as first author
2since 2021 · last 2024
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 4 · 2 since 2021Databases, data management, data science and information retrieval · 1 · 1 since 2021

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Software engineering, system software, and programming languages
1 paper
Operating systems · 100%
Computer architecture, parallel and distributed computing, and storage systems
2 papers
Storage systems · 85% Memory systems · 15%

Topics — the 5 heaviest of 5, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Operating systems › i/o › i/o subsystem
i/o path
0.812024
I/O Passthru: Upstreaming a flexible and efficient I/O Path in Linux · FAST 2024
Operating systems › kernel
linux kernel
0.812024
I/O Passthru: Upstreaming a flexible and efficient I/O Path in Linux · FAST 2024
Storage systems
key-value storage
0.312018
Reducing DRAM footprint with NVM in facebook · EuroSys 2018
Storage systems › i/o architecture › i/o subsystem
storage i/o
0.212024
I/O Passthru: Upstreaming a flexible and efficient I/O Path in Linux · FAST 2024
Memory systems
non-volatile memory
0.112018
Reducing DRAM footprint with NVM in facebook · EuroSys 2018

Methods — techniques the papers use, named apart from their topics

NVM block device integration · 0.3
YearPublicationVenuePosition
2024 I/O Passthru: Upstreaming a flexible and efficient I/O Path in Linux
Kanchan Joshi, Javier González 0006, Krishna Kanth Reddy, Arun George, Simon Andreas Frimann Lund, Jens Axboe
FAST8
2022 Supporting Massive DLRM Inference through Software Defined Memory
abstract
Deep Learning Recommendation Models (DLRM) are widespread, account for a considerable data center footprint, and grow by more than 1.5x per year. With model size soon to be in terabytes range, leveraging Storage Class Memory (SCM) for inference enables lower power consumption. This paper evaluates the major challenges in extending the memory hierarchy to SCM for DLRM, and presents different techniques to improve performance through a Software Defined Memory. We show how underlying technologies such as Nand Flash and 3DXP differentiate, and relate to real world scenarios, enabling from 5% to 29% power savings.
Ehsan K. Ardestani, Changkyu Kim, Luoshang Pan, Jens Axboe, Valmiki Rampersad, Banit Agrawal, Fuxun Yu, Ansha Yu, Trung Le 0003, Hector Yuen, Dheevatsa Mudigere, Shishir Juluri, Akshat Nanda, Manoj Wodekar, Krishnakumar Nair, Maxim Naumov, Chris Petersen 0002, Mikhail Smelyanskiy, Vijay Rao
ICDCS5
2018 Reducing DRAM footprint with NVM in facebook
abstract
Popular SSD-based key-value stores consume a large amount of DRAM in order to provide high-performance database operations. However, DRAM can be expensive for data center providers, especially given recent global supply shortages that have resulted in increasing DRAM costs. In this work, we design a key-value store, MyNVM, which leverages an NVM block device to reduce DRAM usage, and to reduce the total cost of ownership, while providing comparable latency and queries-per-second (QPS) as MyRocks on a server with a much larger amount of DRAM. Replacing DRAM with NVM introduces several challenges. In particular, NVM has limited read bandwidth, and it wears out quickly under a high write bandwidth.
Assaf Eisenman, Darryl Gardner, Islam AbdelRahman, Jens Axboe, Siying Dong, Kim M. Hazelwood, Chris Petersen 0002, Asaf Cidon, Sachin Katti
EuroSys4
2013 Linux block IO: introducing multi-queue SSD access on multi-core systems
abstract
The IO performance of storage devices has accelerated from hundreds of IOPS five years ago, to hundreds of thousands of IOPS today, and tens of millions of IOPS projected in five years. This sharp evolution is primarily due to the introduction of NAND-flash devices and their data parallel design. In this work, we demonstrate that the block layer within the operating system, originally designed to handle thousands of IOPS, has become a bottleneck to overall storage system performance, specially on the high NUMA-factor processors systems that are becoming commonplace. We describe the design of a next generation block layer that is capable of handling tens of millions of IOPS on a multi-core system equipped with a single storage device. Our experiments show that our design scales graciously with the number of cores, even on NUMA systems with multiple sockets.
Matias Bjørling, Jens Axboe, David W. Nellans, Philippe Bonnet
SYSTOR2