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Yoshio Nishi

dblp:132/0398 · DBLP profile ↗
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2ranked-venue papers
0as first author
0since 2021 · last 2014
—ORCID · unresolved

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 1Applied, interdisciplinary, general and emerging computing · 1

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Integrated circuit design · 77% Electronic design automation · 23%

Topics — the 2 heaviest of 2, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Integrated circuit design › semiconductor devices › device scaling
CMOS scaling limits
0.012001
Limits of integrated-circuit manufacturing · Proc. IEEE 2001
Electronic design automation
design methodology
0.012001
Limits of integrated-circuit manufacturing · Proc. IEEE 2001

Methods — techniques the papers use, named apart from their topics

hierarchical modeling · 0.0
YearPublicationVenuePosition
2014 Ab initio modeling of resistive switching mechanism in binary metal oxides
abstract
Binary transition metal oxides TiOx, NiOx, HfOx, AlOx, TaOxhave been recently proposed as possible materials for resistance change based non-volatile memory devices. Currently, a major bottleneck in determining the scalability, retention and endurance of these devices, is the lack of detailed understanding of the resistive switching mechanism. To explain the observed device characteristics the so-called filamentary models have been widely adopted and also extensively investigated theoretically. First, in order to control the forming voltage in these devices the formation energy implications of possible conductive channels has to be evaluated. Ab initio techniques have recently been applied to study conductive filamentary structures characteristic to the “ON” state (or LRS - low resistance state). Next, the atomistic descriptions of the rupturing/dissolution process into the “OFF” state of the memory operation (HRS - high resistance state) needed to be addressed. Based on quantum mechanical calculations, electron and hole trapping effects were shown to have a significant role in the switching process under applied electrical field. While hole injection into oxygen reduced transition metal oxide with a formed filament can favor the dissolution process, electron injection induces filament formation. Then, as possible ways to achieve desired device characteristics, preferential impurity doping in these types of systems has been proposed to favorably affect and control the “ON” - “OFF” transition process.
Blanka Magyari-Köpe, Yoshio Nishi, Katsumasa Kamiya, Moon Young Yang, Kenji Shiraishi
ISCAS3
2001 Limits of integrated-circuit manufacturing
abstract
A methodology is suggested for the study of integrated-circuit manufacturing limits. It is based on a hierarchical view of manufacturing detractors and associates limits with levels in this hierarchy. The methodology is illustrated with examples of steady-state, theoretical, and process limits at today's state of the art as well as example projections to future manufacturing at what may be near the limits of complementary metal-oxide-semiconductor (CMOS) scaling. There are also some speculations on possibilities beyond these limits.
Robert Doering, Yoshio Nishi
Proc. IEEE2