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Dmytro Apalkov

dblp:132/6312 · DBLP profile ↗
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2ranked-venue papers
2as first author
0since 2021 · last 2016
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 1 · 1 first-authorApplied, interdisciplinary, general and emerging computing · 1 · 1 first-author

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Memory systems · 100%

Topics — the 3 heaviest of 3, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Memory systems › non-volatile memory
magnetic random access memory
0.212016
Magnetoresistive Random Access Memory · Proc. IEEE 2016
Memory systems
non-volatile memory
0.212016
Magnetoresistive Random Access Memory · Proc. IEEE 2016
Memory systems › non-volatile memory › magnetic random access memory
STT-MRAM
0.212016
Magnetoresistive Random Access Memory · Proc. IEEE 2016
YearPublicationVenuePosition
2016 Magnetoresistive Random Access Memory
abstract
In this paper, a review of the developments in MRAM technology over the past 20 years is presented. The various MRAM generations are described with a particular focus on spin-transfer torque MRAM (STT-MRAM) which is currently receiving the greatest attention. The working principles of these various MRAM generations, the status of their developments, and demonstrations of working circuits, including already commercialized MRAM products, are discussed.
Dmytro Apalkov, Bernard Dieny, Jon M. Slaughter
Proc. IEEE1
2013 Spin-transfer torque magnetic random access memory (STT-MRAM)
abstract
Spin-transfer torque magnetic random access memory (STT-MRAM) is a novel, magnetic memory technology that leverages the base platform established by an existing 100+nm node memory product called MRAM to enable a scalable nonvolatile memory solution for advanced process nodes. STT-MRAM features fast read and write times, small cell sizes of 6F 2 and potentially even smaller, and compatibility with existing DRAM and SRAM architecture with relatively small associated cost added. STT-MRAM is essentially a magnetic multilayer resistive element cell that is fabricated as an additional metal layer on top of conventional CMOS access transistors. In this review we give an overview of the existing STT-MRAM technologies currently in research and development across the world, as well as some specific discussion of results obtained at Grandis and with our foundry partners. We will show that in-plane STT-MRAM technology, particularly the DMTJ design, is a mature technology that meets all conventional requirements for an STT-MRAM cell to be a nonvolatile solution matching DRAM and/or SRAM drive circuitry. Exciting recent developments in perpendicular STT-MRAM also indicate that this type of STT-MRAM technology may reach maturity faster than expected, allowing even smaller cell size and product introduction at smaller nodes.
Dmytro Apalkov, Alexey Khvalkovskiy, Steven Watts, Vladimir Nikitin, Xueti Tang, Daniel Lottis, Kiseok Moon, Eugene Chen, Adrian Ong, Alexander Driskill-Smith, Mohamad Krounbi
ACM J. Emerg. Technol. Comput. Syst.1