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Nan Liao

dblp:133/2947 · DBLP profile ↗
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7ranked-venue papers
2as first author
0since 2021 · last 2017
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Applied, interdisciplinary, general and emerging computing · 5 · 2 first-authorSystems, architecture and hardware · 2

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
4 papers
Integrated circuit design · 89% Energy-efficient computing · 11%
Network and information security
1 paper
Hardware security and side channels · 87% Cryptographic primitives and cryptanalysis · 13%

Topics — the 10 heaviest of 10, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Integrated circuit design
low-power circuit design
0.632016
Ultralow-power high-speed flip-flop based on multimode FinFETs · Sci. China Inf. Sci. 2016
Ultra-low power dissipation of improved complementary pass-transistor adiabatic logic circuits based on FinFETs · Sci. China Inf. Sci. 2014
Low power adiabatic logic based on FinFETs · Sci. China Inf. Sci. 2014
Integrated circuit design › low-power circuit design
adiabatic logic
0.422014
Ultra-low power dissipation of improved complementary pass-transistor adiabatic logic circuits based on FinFETs · Sci. China Inf. Sci. 2014
Low power adiabatic logic based on FinFETs · Sci. China Inf. Sci. 2014
Hardware security and side channels › fault attacks
differential fault analysis
0.312017
Improving DFA attacks on AES with unknown and random faults · Sci. China Inf. Sci. 2017
Hardware security and side channels
fault attacks
0.312017
Improving DFA attacks on AES with unknown and random faults · Sci. China Inf. Sci. 2017
Integrated circuit design › digital circuit design › sequential circuit design
flip-flop
0.212016
Ultralow-power high-speed flip-flop based on multimode FinFETs · Sci. China Inf. Sci. 2016
Integrated circuit design › semiconductor devices › multi-gate devices
FinFET circuit design
0.212015
Key characterization factors of accurate power modeling for FinFET circuits · Sci. China Inf. Sci. 2015
Energy-efficient computing
power modeling
0.212015
Key characterization factors of accurate power modeling for FinFET circuits · Sci. China Inf. Sci. 2015
Integrated circuit design › semiconductor devices › multi-gate devices
FinFET
0.232016
Ultralow-power high-speed flip-flop based on multimode FinFETs · Sci. China Inf. Sci. 2016
Ultra-low power dissipation of improved complementary pass-transistor adiabatic logic circuits based on FinFETs · Sci. China Inf. Sci. 2014
Low power adiabatic logic based on FinFETs · Sci. China Inf. Sci. 2014
Cryptographic primitives and cryptanalysis › block cipher
AES
0.112017
Improving DFA attacks on AES with unknown and random faults · Sci. China Inf. Sci. 2017
Integrated circuit design › semiconductor devices › multi-gate devices
FinFET technology
0.112015
Key characterization factors of accurate power modeling for FinFET circuits · Sci. China Inf. Sci. 2015

Methods — techniques the papers use, named apart from their topics

power modeling · 0.2
YearPublicationVenuePosition
2017 Improving DFA attacks on AES with unknown and random faults
Nan Liao, Xiaoxin Cui, Dunshan Yu, Xiaole Cui
Sci. China Inf. Sci.1
2016 Ultralow-power high-speed flip-flop based on multimode FinFETs
Xiaoxin Cui, Nan Liao, Dunshan Yu, Xiaole Cui
Sci. China Inf. Sci.3
2015 Key characterization factors of accurate power modeling for FinFET circuits
Kaisheng Ma, Xiaoxin Cui, Nan Liao, Dunshan Yu
Sci. China Inf. Sci.4
2014 High-speed constant-time division module for Elliptic Curve Cryptography based on GF(2m)
abstract
To achieve high performance scalar multiplication arithmetic in Elliptic Curve Cryptography (ECC) based on GF(2m), a high-speed constant-time division module with optimized architecture is proposed in this paper. Modified from the traditional extended Euclidean Great Common Divisor (GCD) division algorithm, the presented algorithm computes a single multiplicative inverse or division in constant m iterations, i.e. m clock cycles, in GF(2m), which obtains a tremendous reduction (specifically more than 50%) on computing time compared with previous works. Combined with the meticulously optimized architecture, this novel division module achieves lower area-time complexity, which makes it an excellent option for high performance ECC design.
Xiaoxin Cui, Nan Liao, Dunshan Yu
ISCAS3
2014 Low power adiabatic logic based on FinFETs
Nan Liao, Xiaoxin Cui, Kaisheng Ma, Dunshan Yu
Sci. China Inf. Sci.1
2014 Ultra-low power dissipation of improved complementary pass-transistor adiabatic logic circuits based on FinFETs
Xiaoxin Cui, Nan Liao, Kaisheng Ma, Dunshan Yu
Sci. China Inf. Sci.3
2013 A Dynamic-Adjusting Threshold-Voltage Scheme for FinFETs low power designs
abstract
In this paper, a novel device/circuit co-design scheme, namely Dynamic-Adjusting Threshold-Voltage Scheme (DATS) for independent-gate mode FinFET circuits has been proposed. The main idea of this scheme is that a pair of back-gate bias of FinFETs is adjusted dynamically to change threshold voltage according to the system operating frequency and operating mode, which could optimize circuit power, especially leakage power. The experimental and simulation result shows that the leakage power dissipation reduced greatly when circuits operate at the lower frequency, and the energy-delay product of FinFET circuits is reduced by 30% approximately.
Xiaoxin Cui, Kaisheng Ma, Nan Liao, Dunshan Yu
ISCAS4