With the advancement of computing systems, the demand for energy-efficient NVMs has increased due to the recent challenges of traditional memory technologies like SRAMs and DRAMs. Thus, alternative NVMs like STT-MRAM have gained significance. However, one of the significant challenges of STT-MRAMs, is their stochastic/unreliable write operations. To address this, a noticeable amount of energy should be applied to the STT-MRAM cell to perform a reliable write operation. While reliable write operation in STT-MRAMs matter, there are many situations in which the applied write energy is more than enough for the required reliability level. In this research, we proposed VS-ReLEnT to balance the reliability and energy consumption of STT-MRAMs cache write operations. In VS-ReLEnT the write voltage actuation knob of the STT-MRAM-based cache is controlled by a Reinforcement Learning (RL) algorithm. Accordingly, based on the contents that will be written on the STT-MRAM cache block, the suitable voltage is chosen by VS-ReLEnT and applied to the cells. This allows the adjustment of each level of VS-Relent to the most suitable reliability level. The simulation results demonstrate an average energy improvement of 16% compared to the golden case, where all data is written with the highest reliability level while preserving reliability in the system. Conversely, the area overhead and imposed leakage energy of VS-ReLEnT show only a marginal increase of 0.24% and 0.21%, respectively.

Energy harvesting is considered to be a substitute for batteries in many modern systems. Systems based on energy harvesting receive environmental energies from sources such as sun, radio frequency, wind, vibration, etc, and convert them to electrical energy to be used by the capacitor of the system or feed the CPS system directly. Despite its advantages, energy harvesting comes with some limitations, such as the instability of the received energy, which means that the energy may not be received for a moment due to environmental conditions during energy harvesting. Therefore, due to not receiving enough energy, the system function may face problems, which can lead to system shutdown and data loss. To prevent program execution interruption caused by frequent power interruptions in systems based on energy harvesting, these systems use NVP. Saving the state in the NVP is done through non-volatile registers and memories that can hold the contents until the power is restored. However, systems based on energy harvesting and NVPs also have challenges such as frequent backups’ energy consumption, slow program forward progress, and loss of data. In this paper, we propose TVTAC, a framework for energy harvesting-based NVP CPS systems. TVTAC modifies conventional NVP’s cache architecture to efficiently work with newly introduced operational mode to prevent unnecessary backup operations. Furthermore, TVTAC is equipped with an NVP’s specific approximation unit that controls the approximation knobs during the approximate data cache accesses in order to save more energy. The simulation results show that TVTAC improves forward progress by 28% in the best case and 12% on average, compared to similar methods. From an energy consumption perspective, TVTAC reduces energy consumption by 43.5% in the best case and 28.5% on average.

RPL is introduced to conduct path selection in Low-power and Lossy Networks (LLN), including IoT. A routing policy in RPL is governed by its objective function, which corresponds to the requirements of the IoT application, e.g., energy-efficiency, and reliability in terms of Packet Delivery Ratio (PDR). In many applications, it is not possible to connect the nodes to the power outlet. Also, since nodes may be geographically inaccessible, replacing the depleted batteries is infeasible. Hence, harvesters are an admirable replacement for traditional batteries to prevent energy hole problem, and consequently to enhance the lifetime and reliability of IoT networks. Nevertheless, the unstable level of energy absorption in harvesters necessitates developing a routing policy, which could consider harvesting aspects. Furthermore, since the rates of absorption, and consumption are incredibly dynamic in different parts of the network, learning-based techniques could be employed in the routing process to provide energy-efficiency. Accordingly, this paper introduces LANTERN; a learning-based routing policy for improving PDR in energy-harvesting IoT networks. In addition to the rate of energy absorption, and consumption, LANTERN utilizes the remaining energy in its routing policy. In this regard, LANTERN introduces a novel routing metric called Energy Exponential Moving Average (EEMA) to perform its path selection. Based on diversified simulations conducted in Cooja, with prolonging the lifetime of the network by$5.7\times $, and mitigating the probability of energy hole problem, LANTERN improves the PDR by up to 97%, compared to the state-of-the-art. Also, the consumed energy per successfully delivered packet is reduced by 76%.

Mobile portable embedded devices are becoming an integral part of our daily activities in the vision of Internet of Things (IoT). Nevertheless, due to lack of mobility support in the IPv6 routing protocol for low-power and lossy networks (RPLs), which is standardized for multihop IoT infrastructures, providing reliable communications in terms of packet delivery ratio (PDR) in mobile IoT applications has become significantly challenging. While several studies tried to enhance the adaptability of RPL to network dynamics, their utilized routing metrics have prevented them from establishing long-lasting reliable paths. Furthermore, the stochastic parent replacement policy in the standard version of RPL has intensified this challenge. Aside from this, due to the existing tradeoff between reliability and power efficiency, most of the existing approaches have only concentrated on one of these concerns without paying attention to the other one. To address these issues, this article introduces ARMOR, a routing mechanism built upon RPL, which employs a novel mobility-aware routing metric, i.e., time to reside (TTR), and a corresponding parent replacement policy. According to the motion characteristics of the mobile objects, TTR provides an estimation of how long the nodes will be in the transmission range of each other. This enables ARMOR to select nodes, which provide longer connection period and consequently higher reliability. In comparison with the state of the art, while keeping the power consumption constant, ARMOR significantly improves the amount of PDR in the network by up to$2.5\times $, while it enhances the reliability against the original version of this protocol by up to$4.2\times $.

Reliability of routing mechanisms in wireless networks is typically measured with Packet Delivery Ratio (PDR). Basically, PDR is reported with an optimistic assumption that the topology is fully constructed, and the nodes have started their packet transmission. This is despite the fact that prior to being able to transmit packets, nodes must first join the network, and then try to keep connected as much as possible. This is a key factor in the overall reliability provided by the routing protocols, especially in mobile IoT applications, where disconnections occur frequently. Nevertheless, there is a lack of appropriate metrics, which could evaluate the routing mechanisms from this perspective. Accordingly, this paper introduces attachability; a new metric for evaluating the capability of routing protocols in assisting the mobile or stationary nodes in joining, and maintaining their connections to the network. Our newly proposed metric is calculated via Markov chain analysis along with the sample frequency-based estimating technique. To evaluate attachability, we have simulated a mobile IoT infrastructure, and conducted a comprehensive set of experiments on different versions of the IPv6 Routing Protocol for Low-power and lossy networks (RPL). Based on our observations, attachability is significantly dependent on the employed metrics and path selection policies in the routing mechanisms. Among the three different versions of RPL, including the original version (ORPL), which is standardized for stationary IoT applications, and two mobility-aware versions, i.e., MARPL, and OMARPL, OMARPL showed up to 42%, and 10% of improvement in terms of attachability against ORPL, and MARPL, respectively.

Energy consumption is a major challenge in IoT devices, which was aimed to be improved by employing energy-efficient objective functions (OFs) in the structure of the RPL routing protocol. Meanwhile, the majority of the existing OFs mainly perform the parent selection based on the gathered information from the routing layer. Nevertheless, based on our investigations, there exists a series of transmission operations in the medium access control (MAC) layer, which significantly affects the energy consumption in IoT devices. Therefore, in this article, we propose ELITE, an energy-efficient cross-layer OF, which introduces a novel routing metric, called strobe per packet ratio (SPR). SPR indicates the number of transmitted strobes per packet due to radio duty cycling (RDC) policies in the MAC layer. This newly defined metric, which has been designed to be coupled with asynchronous MAC protocols, could be differentiated node by node and based on the existing relative phase shift between the communicating nodes. In this regard, the ELITE tries to select a path, which imposes less number of strobe transmissions to its nodes. According to the evaluation results, while ELITE could reduce the average amount of required strobes per packet by up to 25%, it can significantly improve the average amount of consumed energy in an IoT node by up to 39% compared to its counterpart OFs.

The stochastic switching feature of Spin-Transfer Torque Magnetic RAM (STT-MRAM) provides an attractive knob to trade quality for energy consumption in approximate computing applications. Indeed, the quality of STT-MRAM functionalities (mainly write operation) is increased by consuming more energy to achieve a more stable write. On the other hand, in approximate computing applications, we do not need 100 percent quality for all of the data. Accordingly, in recent years, several approaches have been proposed to find a balance between output threshold quality and energy consumption in approximate computing applications employing STT-MRAM on-chip memories. While approximate computing application output qualities are highly affected by the fluctuations of the environmental-conditions or input variations, none of the previously proposed approaches have considered the effects of these fluctuations on the output quality. In this article, we propose NOSTalgy, a closed-loop cross-layer approach to dynamically trade off the quality of STT-MRAM based cache memories for energy saving in approximate computing applications. NOSTalgy utilizes a feedback managed fine-grained cache-line-level actuation knobs with different levels of quality for individual write accesses. These knobs are adjusted with the support of the operating system and programmer at run-time. Our experimental results using a set of benchmarks show that NOSTalgy satisfies the output quality thresholds while delivering up to 52 percent energy savings with negligible performance and area overheads.

STT-MRAM is regarded as an extremely promising NVM technology for replacing SRAM-based on-chip memories. While STT-MRAM memories benefit from ultra-low leakage power and high density, they suffer from some reliability challenges, namely, read disturbance, write failure, and retention failure. The write failure; storing a wrong value in an STT-MRAM cell during a write operation, is the most crucial reliability challenge. In this article, we propose ROCKY; a robust architecture equipped with efficient replacement policies for STT-MRAM-based cache memory hierarchy to improve the robustness of STT-MRAM part against the write failures. ROCKY reduces susceptible transitions in STT-MRAM cache memories leading to more reliable STT-MRAM write operations. The simulation results through comparison with traditional cache memory hierarchy demonstrate ROCKY decreases the WER of STT-MRAM cache memories by up to 35.4 percent while imposing less than 1 percent performance overhead to the system.

Tackling the dark silicon problem in a heterogeneous multicore system, the temperature constraints across the system should be addressed carefully by assigning a proper set of tasks to a pool of the heterogeneous cores during the run-time. When such a system is utilized in a reliable/real-time application, the reliability/timing constraints of the application should also be augmented to the temperature constraints and make the tasks mapping problem more and more complex. To solve the mapping problem in such a situation, we propose READY; an online reliability- and deadline-aware mapping and scheduling algorithm for heterogeneous multicore systems. READY utilizes an adaptive power constraint (as a metric for temperature measurement) that is updated according to the number and position of the active cores on the chip. READY, first, attempts to meet the reliability target of the system by improving the reliability of each task. Then, it performs the mapping and scheduling of the tasks on cores of different islands, so that the peak power and timing constraints are met. The simulation results illustrate that while READY guarantees the timing constraints and meets reliability targets, it improves the peak-power-aware system schedulability (chip performance) by 23.77% (up to 40.69%).

Spin transfer torque magnetic RAM (STT-MRAM) technology is one of the most promising alternative for static RAM (SRAM) for implementing on-chip memories. Compared with SRAMs, STT-MRAMs benefit from higher density and near-zero leakage power, nonetheless they impose high energy consumption for reliable write operations. However, in many applications, absolute data integrity is not required; thus, acting on the current applied in the write operations may represent a novel knob for disciplined approximate computing to obtain energy saving with a minimal quality loss in applications' outputs. This article proposes CAST, a hardware/software approach to adjust the energy/quality of write operations in STT-MRAM caches in multicore systems based on the content of requested write operations. CAST utilizes fine-grained cache-line-level actuation knobs with different levels of quality for individual write operations. This unique feature of STT-MRAMs allows to avoid interapplication actuation interference suffered by SRAMs, and makes the approach particularly suitable for systems running multiple applications with mixed accuracy sensitivity. Moreover, CAST exploits another peculiarity of STT-MRAMs represented by the asymmetry and transition-dependency of the write error rate, to further tune in a fine-grained manner the write current to achieve an additional energy saving, even in full-accurate applications. Our evaluations on workloads of full-approximate, mixed-criticality, and full-accurate applications demonstrate up to 57%, 34%, and 21% energy savings over a baseline STT-MRAM cache, respectively, with an acceptable quality of the generated outputs.

Spin-Transfer Torque Magnetic Random Access Memory (STT-MRAM) is a promising alternative to SRAM in cache memories. However, STT-MRAMs face with high probability of write errors due to its stochastic switching behavior. To correct the write errors, Error-Correcting Codes (ECCs) used in SRAM caches are conventionally employed. A cache line consists of several codewords and the data bits are selected in such a way that the maximum correction capability is provided based on the error patterns in SRAMs. However, the different write error patterns in STT-MRAM caches leads to inefficiency of conventional ECC configurations. In this paper, first we investigate the efficiency of ECC configurations and demonstrate that the vulnerability of codewords in a cache line varies by up to 17x. This variation means that, while some words are overprotected, some others are highly probable to experience uncorrectable errors. Then, we propose an ECC bit selection scheme, so-called ORIENT, to reduce the vulnerability variation of codewords to 1.4x. The simulation results show that conventional ECC configuration increases the write error rate by up to about 64.4% compared with the optimum ECC bit selection, whereas this value for ORIENT is only 4.5%.

With the recent development in Non-Volatile Memory (NVM) technologies, several studies have suggested using them as an alternative to SRAMs in on-chip caches. However, limited endurance of NVMs is a major challenge when employed in the caches. This paper proposes a data manipulation technique, so-called Wearout Informed Pattern Elimination (WIPE), to improve the endurance of NVM-based caches by reducing the activity of frequent data patterns. Simulation results show that WIPE improves the endurance by up to 93% with negligible overheads.

Emerging STT-MRAM memories are promising alternatives for SRAM memories to tackle their low density and high static power consumption, but impose high energy consumption for reliable read/write operations. However, absolute data integrity is not required for many approximate computing applications, allowing energy savings with minimal quality loss. This paper proposes QuARK, a hardware/software approach for trading reliability of STT-MRAM caches for energy savings in the on-chip memory hierarchy of multi- and many-core systems running approximate applications. In contrast to SRAM-based cache-way-level actuators, QuARK utilizes fine-grained cache-line-level actuation knobs with different levels of reliability for individual read and write accesses which are unique to STT-MRAM and suitable for systems running multiple applications with mixed accuracy sensitivity, thus avoiding interapplication actuation interference. Our experimental results with a set of recognition, mining and synthesis (RMS) benchmarks demonstrate up to 40% energy savings over a fully-protected STT-MRAM cache, with negligible loss in the quality of the generated outputs.

Due to serious problems of SRAM-based caches in nano-scale technologies, researchers seek for new alternatives. Among the existing options, STT-RAM seems to be the most promising alternative. With high density and negligible leakage power, STT-RAMs open a new doorto respond to future demands of multi-core systems, i.e., large on-chip caches. However, several problems in STT-RAMs should be overcome to make it applicable in on-chip caches. High probability of write error due to stochastic switching is a major problem in STT-RAMs. Conventional Error-Correcting Codes (ECCs) impose significant area and energy consumption overheads to protect STT-RAM caches. These overheads in multi-core processors with large last-level caches are not affordable. In this paper, we propose Asymmetry-Aware Protection Technique (A2PT) to efficiently protect the STT-RAM caches. A2PT benefits from error rate asymmetry of STT-RAM write operations to provide the required level of cache protection with significantly lower overheads. Compared with the conventional ECC configuration, the evaluation results show that A2PT reduces the area and energy consumption overheads by about 42 and 50 percent, respectively, while providing the same level of protection. Moreover, A2PT decreases the number of bit switching in write operations by 28 percent, which leads to about 25 percent saving in write energy consumption.

ScratchPad Memory (SPM) is an important part of most modern embedded processors. The use of embedded processors in safety-critical applications implies including fault tolerance in the design of SPM. This paper proposes a method, called FTSPM, which integrates a multi-priority mapping algorithm with a hybrid SPM structure. The proposed structure divides SPM into three parts: 1) a part is equipped with Non-Volatile Memory (NVM) which is immune against soft errors, 2) a part is equipped with Error-Correcting Code, and 3) a part is equipped with parity. The proposed mapping algorithm is responsible to distribute the program blocks among the above three parts with regards to their vulnerability level. The simulation results demonstrate that the FTSPM reduces the SPM vulnerability by about 7x in comparison to a pure SRAM-based SPM. In addition, the dynamic energy consumption of the proposed method is 77% and 47% less than that of a pure NVM-based SPM and a pure SRAM-based SPM, respectively.