We present an open-source calibration methodology for Sky130 CMOS at $\mathbf{4 ~ K}$, focusing on robust initial extraction of threshold voltage (VTH0) and slope factor (n) via the SEKVE parameter-extraction tool. To address measurement noise, a partial Z-score filter is applied to the raw data, reducing extraction errors from above 10% to under 2%. These refined parameters then feed into an iterative BSIM4 calibration using IceMOS. As a result, the final calibrated Sky130 models achieve an accuracy in the strong inversion region with median error percentages of 9.49% for PMOS and just 1.11% for NMOS. Transconductance $g_{m}$ calibration is similarly precise with median errors of 5.95% and 2.46% for PMOS and NMOS, respectively, in the strong inversion region. By separating the SEKV-E and IceMOS steps yet integrating them into a fully open-source flow (including Docker-based ngspice simulations), our approach significantly minimizes manual intervention. The Sky130-compatible IceMOS scripts, Z-score routines, and calibrated device models are publicly available, reinforcing the open-source ecosystem for Cryo-CMOS research.

The analysis and simulation of a novel approach to achieve Capacitive Digital-to-Analog Converter (CDAC) mismatch error shaping using the traditional Data Weighted Averaging (DWA) algorithm is presented. The approach includes dissociating the ADC/DAC processes when extracting the quantization error in a Noise Shaping Successive Approximation Register (NS SAR) architecture. The proposed idea is implemented and validated with behavioral simulations in Matlab®-Simulink® of a 10-bit 3rdorder NS SAR ADC, showing a first-order mismatch error shaping in the presence of CDAC mismatch.

This paper introduces a programmable switch supply comparator that uses a programmable reservoir capacitor to achieve a reduced effective supply voltage during the decision phase. This comparator achieves up to 50% power consumption reduction against the conventional dynamic comparator. Fabricated in 65nm CMOS, the silicon results of the PMOS-input programmable comparator show programmable power consumption and energy efficiency ranging from 2.7 - 4.1μW and 0.22 - 0.5pJ/conv, respectively. Similarly, the input-referred noise can be programmed from 100 - 180μVrms. Additionally, the power (energy efficiency) and input-referred noise can be programmed at any clock cycle, making this design an ideal solution for the two-comparator SAR ADC architecture.

This paper presents behavioural modelling and analysis of Error Feedback (EF) SAR ADCs. The capacitor array model proposed here is based in charge equations, which allows accurate modelling of the feedback in EF-SARs. It also introduces models for the feedback amplifier, including offset, non-linear gain, thermal and flicker noise, as well as sampled kT/C noise for switches and reference noise. The proposed models are implemented and validated in Matlab̅ Simulink̅, showing results with accuracy comparable to transistor-level simulations and simulation times several orders of magnitude faster.

This paper presents a toolbox for the behavioral simulation of SAR ADCs in Simulink®. The models include the most limiting circuit effects such as sampled thermal noise, capacitor mismatch, finite settling, comparator noise and offset. A user friendly interface is also included to allow study and high-level design of SAR ADCs, which is illustrated by means of a design example. It is also shown that the proposed toolbox is several orders of magnitude faster than electrical simulators, while keeping a high accuracy.

This paper discusses design considerations of LC-based bandpass continuous-time ΣΔ modulators intended for the analog-to-digital conversion of radio-frequency signals in software-defined-radio receivers. A top-down high-level synthesis methodology - based on the combination of undersampling techniques, programmable notch frequency and adequate selection of loop-filter coefficients - is presented to design efficient modulator architectures, which can be adapted to fulfill the requirements of diverse wireless communication standards, while keeping stability and robustness to circuit errors. Main architectureand circuit-level design issues are analyzed, considering diverse case studies based on Gm-LC resonators and different kinds of digital-to-analog converters. Time-domain simulations validate the presented approach1.

Classical decimation structures usually use comb filters at first stage due to the simplicity of comb filters. However, comb filters cannot satisfy high performance demands of state-of-the-art Sigma-Delta (ΣΔ) analog-digital converters (ADCs). Some possible solutions are comb based structures which are power and area efficient and posses an improved magnitude characteristic. The principal issues in the comb-based filter design are: power and area efficiency, high alias rejection and approximately flat passband characteristic, considering also high values of the decimation factors. In this paper we first review the new trends in ΣΔ ADCs and demands for the decimation block design. Next we review power and area efficient structures. The methods to improve the alias rejection of comb filters, as well as the methods for the compensation for the comb passband droop, and those strategies which simultaneously improve the alias rejection and the passband droop are reviewed in the following. Finally we review the multirate decimation structures.

This paper introduces a power and area efficient comb-based decimation structure, particularly suited for high values of decimation factors which are a power of two. The proposed topology has two stages, where the first stage is in a non-recursive form and the second one is in a recursive form (CIC filter). Moreover, a slight modification of the proposed decimator structure is presented in order to obtain an improved alias rejection. Simulation results are shown to validate the proposed approach.