Conventional deep learning (DL) model compression methods affect all input samples equally. However, as samples vary in difficulty, a dynamic model that adapts computation based on sample complexity offers a novel perspective for compression and scaling. Despite this potential, existing dynamic techniques are typically monolithic and have model-specific implementations, limiting their generalizability as broad compression and scaling methods. Additionally, most deployed DL systems are fixed, and unable to adjust once deployed. This paper introduces DyCE, a dynamically configurable system that can adjust the performance-complexity trade-off of a DL model at runtime without needing re-initialization or re-deployment. DyCE achieves this by adding exit networks to intermediate layers, thus allowing early termination if results are acceptable. DyCE also decouples the design of exit networks from the base model itself, enabling its easy adaptation to new base models. We also propose methods for generating optimized configurations and determining exit network types and positions for dynamic trade-offs. By enabling simple configuration switching, DyCE enables fine-grained performance-complexity tuning in real-time. We demonstrate the effectiveness of DyCE through image classification tasks using deep convolutional neural networks (CNNs). DyCE significantly reduces computational complexity by 26.2% for ResNet 152 , 26.6% for ConvNextv2 tiny and 32.0% for DaViT base on ImageNet validation set, with accuracy reductions of less than 0.5%. • Effectively compress the computational complexity of deep learning models. • Dynamically Scale any AI model and select a complexity-performance tradeoff point for the model in run-time. • Enable early exiting on any existing deep learning models by attaching tiny exits. • Generates the best early-exit configuration in a multi-exit system for various trade-off preferences.

This paper introduces TinySaver, an early-exit-like dynamic model compression approach which employs tiny models to substitute large models adaptively. Distinct from traditional compression techniques, dynamic methods like TinySaver can leverage the difficulty differences to allow certain inputs to complete their inference processes early, thereby conserving computational resources. Most existing early exit designs are implemented by attaching additional network branches to the model’s backbone. Our study, however, reveals that completely independent tiny models can replace a substantial portion of the larger models’ job with minimal impact on performance. Employing them as the first exit can remarkably enhance computational efficiency. By searching and employing the most appropriate tiny model as the computational saver for a given large model, the proposed approaches work as a novel and generic method to model compression. This finding will help the research community in exploring new compression methods to address the escalating computational demands posed by rapidly evolving AI models. Our evaluation of this approach in ImageNet-1k classification demonstrates its potential to reduce the number of compute operations by up to 90%, with only negligible losses in performance, across various modern vision models.

This paper proposes a time-domain mixed-signal computing architecture for Matrix-Vector Multiplication suited for embedded in-memory computing applications. The system leverages the low data rate of sensors’ data in embedded AI applications to target an energy-efficient implementation of the matrix-vector multiplication array. The mixed-signal computing scheme relies on incremental time-domain multiply-and-accumulate operations using switched current sources. The concept is demonstrated on a 28nm FDSOI prototype chip of a 100$\times $4 compute array that shows a 15.8TOPS/W energy efficiency for 5-bit MAC operations. Extrapolating the array to 100$\times $100 computing units leads to a 99.2TOPS/W energy efficiency.

Sensor Networks (SN) could be defined as networks of autonomous devices that can sense and/or act on physical or environmental conditions cooperatively. In sensor networks, data is typically sensed and sent toanaggregator thatwill process it with local AI or send it to a cloud with larger AI. This centralized architecture has drawbacks such as the aggregator having to receive and process a potentially huge amount of data, which results in power consumption that can be significant. In addition, the transmission of all the sensor data results in extra consumption of energy due to communication. To reduce the impact of this last point, on-edge computing allows data to be pre-processed at the sensor level. It is often used in the architecture of distributed sensor networks in which each node receives data from other nodes in the network and processes it with its local data. In this work, a distributed sensor network model aims to solve this problem while reducing the impact of data transmission on energy consumption. The proposed model is able to reduce the number of transmitted bits per node by 90% in a node-to-node directed communication scenario. It is also capable of working with different AI paradigms depending on the required balance between energy consumption, application configurability, and accuracy. Finally, this model is capable of converging even in a network without complete interconnections between nodes.

Cardiovascular diseases can be detected early by analyzing the electrocardiogram of a patient using wearable systems. In the context of smart sensors, detecting arrhythmias with good accuracy and ultra-low power consumption is required for long-term monitoring. This paper presents a novel cardiac arrhythmia classification method based on antidictionaries. The features are sequences of consecutive slopes generated from the input signal's event-driven processing. The proposed system shows an average detection accuracy of 98% while offering an ultra-low complexity. This antidictionary-based method is also particularly suited to imbalanced datasets since the antidictionaries are created exclusively from heartbeats classified as normal beats.

In this article, non-uniformly sampled electrocardiogram (ECG) signals obtained from level-crossing analog-to-digital converters (LC-ADCs) are analyzed for event-driven classification and compression performance. The signal compression results show that it is important to assess the distortion in eventdriven signals when simulating LC-ADC models, especially at lower resolutions and larger quantization steps. The effects of varying the LC-ADC parameters for the application of cardiac arrhythmia classifiers are also assessed using an artificial neural network (ANN) and the MIT-BIH Arrhythmia Database. In comparison with uniformly-sampled data, it is possible to achieve comparable classification accuracy at a much lower complexity with event-driven ECG signals. The results show the best eventdriven model achieves over 97% accuracy with 79% reduction in ANN complexity with signal-to-distortion ratio (S/D)>21dB. For S/D<; 21dB, the best event-driven model achieves 93% accuracy with a 96% reduction in ANN complexity. An open-source event-driven arrhythmia database is also presented.

Clique-based neural networks implement low-complexity functions working with a reduced connectivity between neurons. Thus, they address very specific applications operating with a very low energy budget. This paper proposes a flexible and iterative neural architecture able to implement multiple types of clique-based neural networks of up to 3968 neurons. The circuit has been integrated in a ST 65-nm CMOS ASIC and validated in the context of ECG classification. The network core reacts in 83ns to a stimulation and occupies a 0.21mm2silicon area.

To operate under severe energy constraints, clique-based neural networks are good candidates. They benefit from a reduced exchange of information between low-complexity processing units with no performance degradation. This paper proposes a modular, flexible and scalable architecture validated by an ST 65-nm CMOS ASIC implementation for a 30-neuron clique-based neural network circuit. With 0.8V power supply, 150nA unitary current and a low performance degradation, the neuron energy consumption is reduced to only 7fJ per synaptic event. The network occupies a 41,820μm2 silicon area.

Encoded Neural Networks (ENN) associate low-complexity algorithm with a storage capacity much larger than Hopfield Neural Networks' (HNN) for the same number of nodes. They are thus promising for implementing large scale neural networks mimicking the functioning of the human brain. The implementation of such a network on chip requires reducing the power consumption of the nodes to the femtojoule range to compare to human brain figures. Moreover, the circuit area must be reduced as much as possible. To address these challenges, this paper proposes a subthreshold analog ENN designed for the ST 65nm CMOS process. The designed circuit accepts power supply between 0.3V and 0.86V with currents below 300nA. In a network of 30 computation nodes, it yields a 32fJ energy consumption per decoding per node. The ENN converges only 21ns after being stimulated. Finally, the node core, i.e. without synapse, has a surface area of only 9.5µm2, and each synapse 3.6µm2.

Encoded neural networks mix the principles of associative memories and error-correcting decoders. Their storage capacity has been shown to be much larger than Hopfield Neural Networks'. This paper introduces an analog implementation of this new type of network. The proposed circuit has been designed for the 1V supply ST CMOS 65nm process. It consumes 1165 times less energy than a digital equivalent circuit while being 2.7 times more efficient in terms of combined speed and surface.