DataFrame libraries are widely adopted in data science for their flexible, Pythonic interfaces, but their fragmented APIs and unstructured query patterns limit systematic optimization. Existing work has explored parallel execution or SQL-style logical rewrites, yet these approaches fall short in capturing DataFrame-specific semantics and Python control-flow context. We present FORTE, the first online, source-to-source query optimizer that unifies multiple DataFrame libraries under a shared intermediate representation (DFL). DFL makes DataFrame semantics explicit, enabling composable and portable rewriting rules such as user-defined function (UDF) lifting/lowering, loop lifting, and API tuning, alongside classical rewrites (e.g., predicate pushdown). FORTE employs a lightweight, learned cost model and greedy search to apply these rewrites with negligible overhead, while supporting both intra-library optimization and cross-library transpilation. Our evaluation on TPC-H workloads and real-world Kaggle/GitHub workloads shows that FORTE consistently delivers substantial speedups—up to 52.53× (3.7× on average) across Pandas, Modin, Polars, and Pandas-on-Spark—demonstrating that online, IR-guided rewriting can significantly outperform existing DataFrame engines and rewriters, while enabling cross-library retargetability.

We present an LC-based hybrid sub-sampling phase-locked loop (PLL). A novel tri-state integral path is applied to reduce the loop filter (LF) area and eliminate ripples on the control signals. The effectiveness of the proposed technique is compared with type-II hybrid PLL and PLL using delta-sigma modulator. The 24.6-29.6GHz PLL instance implemented in 28-nm planar process achieves RMS jitter of 44fs and -254.8dB FOM and consumes power of 17mW from a 0.9/0.95V supply.

We present a ring-oscillator-based sub-sampling phase-locked loop (PLL) using a generator-based design flow. A hybrid loop with a delta-sigma ($\Delta \Sigma$) modulator is applied to reduce the loop filter (LF) area and the control ripple. The generator automatically produces the ring oscillator and PLL to meet the provided specifications. The 10-GHz PLL instance implemented in 28-nm planar process achieves RMS jitter of}299.5 fs and power of 9.9 mW from a 1-V supply.

This paper presents a cellular RF transmitter architecture based on a six-port modulator, and its application in an OFDM environment. This paper shows a possibility to apply RF transmitter based on six-port modulator to an OFDM environment, and also it shows that previous works which were limited to single-carrier transmission can be extended to multi-carrier transmission application. The proposed six-port modulator consists of three hybrid couplers, a Wilkinson power combiner, and CMOS Ron resistor banks, which can be favorably integrated into a 2.4 × 1.8 mm2chip area. It obviates the need for DACs and mixers, which are essential components in conventional RF transmitters. A prototype chip was fabricated using the TSMC 0.13 μm CMOS process. Its performance was evaluated and verified by transmitting OFDM signals following the 3GPP standard at 1.84 GHz carrier with 1.4 MHz bandwidth. The prototype chip achieved EVM of 16.1 % and 14.6 % for QPSK and 16-QAM transmissions, respectively. This is a report implementing a new RF transmitter based on a six-port modulator for multiple subcarriers in an OFDM environment, where I/Q signals have 8.3 equivalent number of bits resolutions, respectively.

This study presents analyses of the feasibility for the 28 GHz band with a comprehensive overview of important channel parameters. A channel measurement system with a time synchronisation scheme is also introduced which is a sliding correlator channel sounder using 250 Mcps (Mega‐chips‐per‐second) pseudo‐random noise sequences. The system enables the observation of the behaviour of 28 GHz wave propagation not only to use of forming narrow beams in certain directions (classical narrow beam beamforming) but also omni‐likely. This novel synchronised system makes it possible to analyse the wideband channel characteristics. The outdoor channel measurements are conducted considering various features such as foliage effects, signal outage, path loss and outdoor‐to‐indoor conditions. Furthermore, the spatial channel modelling for omni‐like observations with temporal characteristics is firstly interpreted through analysing the essential channel modelling parameters, including the number of clusters, excess delay, root‐mean‐square (RMS) delay spread, power delay spectrum, and angular spread. In the authors’ measurements, the average number of clusters was 2.41 with standard deviation of 1.44. The average RMS delay spread was 36.06 ns with standard deviation of 46.73 ns. Furthermore, the mean values of the RMS azimuth spreads of the angle of departure and arrival were 6.65° and 24.04°, respectively.

This paper reports a voltage-controlled oscillator (VCO)-based single-loop continuous-time (CT) ΣΔ analog-to-digital converter (ADC) that does not need any OTA-based analog integrator. It achieves the second-order noise shaping by cascading two VCO-based integrators and removing the sampling operation in the first VCO-based integrator. Behavioral simulations confirm the validity of the proposed ADC architecture.

This paper presents the design of a first-order close-loop VCO based ΔΣ ADC. Unlike other VCO based ADC, it does not contain operational amplifier which is power hungry and scaling unfriendly. Also, by using two VCOs referring to each other, it has an intrinsic DEM capability that improves SNDR degradation caused by mismatches in the feedback DAC. The design is low power and area efficient. A prototype is designed in the 0.13um CMOS technology with a power supply of 1.5V. The input signal bandwidth is 10MHz. In SPICE simulation, 70dB of SNDR is achieved while consuming only 5.6mW.