A fully integrated and reconfigurable octa-channel bio-signal acquisition system-in-package (SiP), which enables the wireless measurement of electromyography (EMG), electrocardiogram (ECG), or electroencephalography (EEG), is presented in this article. Each chiplet contains an analog front end in combination with a channel-selection multiplexer, a successive-approximation-register analog–digital converter (SAR-ADC), an ultra-wideband transmitter (UWB-TX), a low-power on-chip crystal-based clock generation circuit, and a low-dropout voltage regulator, including voltage reference. The die occupies an area of 3.64 mm2in a 180-nm 1P6M CMOS technology. A flexible acquisition of bio-potentials is possible due to the rail-to-rail (R–R) input dc tolerance and multiple bandwidth and gain modes (0.2–128/512/2048 Hz, and 19.9–53.1 dB, respectively). In addition, a low total harmonic distortion (THD) of$-51.1$dB of the bio-signal acquisition analog front end (Bio-AFE) for bio-signal relevant levels and a high signal-to-noise-and-distortion ratio (SNDR) of 83.0 dB of the SAR-ADC result in a high linearity of the recorded bio-signals. A low input-referred noise ranging from 2.9 to 7.1$\mu$Vrms, together with a high differential input impedance of 216 M$\Omega$and a common-mode rejection ratio (CMRR) of 81.6 dB, is essential for the acquisition of the low-amplitude bio-signals. The low-power consumption of 0.37–1$\mu$W per channel (mode-dependent) of the Bio-AFE and that of 1.22$\mu$W per channel of the SAR-ADC, both from a 1-V supply, enable battery-or RF-powered applications in a small form factor.

This work demonstrates how adiabatic switching can be used to reduce the power consumption in N-path-filter based receiver designs. Our approach eliminates the common drawback of switching a relatively large gate capacitance at RF and the resulting power consumption is removed through adiabatic switching within the N-path. To maintain good filtering and switching performance while avoiding interferer pulling of the oscillator, an integrated class-F VCO with enriched 3rd order harmonic operating at 2$\times$ the RF input frequency is used for divider-based IQ generation. Steering switches directly connect the IQ mixer switches to the oscillator tank for a tuned drive. To prove the principle, a test-chip was fabricated in a 1P6M180nm CMOS technology. The receiver, including an LNA and PLL, consumes 5.2mW from a 1.2V supply. It provides a gain of 17.7 dB and a narrowband 1. 3MHz filtering within the 868 MHz and 915MHz SRD bands. An integrated 50 $\Omega$ input match is used, trading increased NF for a minimum number of external components.

This brief presents a versatile thermal sensor, which features explicit simplicity on both circuit and system level. High accuracy without the need for calibration is possible by using the NPN bipolar device, available from a triple-well process. Combining the current-mode principle with an active integrator, the architecture can provide the temperature information directly through the duty-cycle of a single output signal. Not only the generation of PTAT and CTAT signals, but also the processing and basic A/D conversion is performed in the same feedback loop. This results in a robust and compact solution, that is independent from external clock or other control signals. A prototype sensor occupies only 2475 μm2silicon area in 16nm FinFET and consumes 30 μA at 0.95 V supply voltage. Across the consumer range, it achieves an accuracy of ± 1.56 °C (3σ) without calibration and a typical conversion speed of 40kS/sec., which are among best-in- class figures.

State-of-the-art radio frequency transceivers for mobile communication devices suffer from transmitter-to-receiver (Tx-Rx) leakage in frequency division duplex operation, which, in combination with further non-idealities in the analog frontend, may lead to diverse self-interference (SI) effects. Digital as well as mixed-signal architectures have been proposed for self- interference cancellation. In this work we present a digitally intensive mixed-signal approach, where a low-cost auxiliary receiver senses the leaked Tx-signal. Firstly, the sensed signal is used to adaptively estimate the leakage channel, whereas in a second step a cleaned version of the leaked Tx-signal is reconstructed digitally. This reconstructed Tx-leakage signal is then used as input for a low complex adaptive interference cancellation unit to suppress modulated spurs or intermodulation distortions. We show that this approach allows to significantly relax the analog auxiliary receiver specifications, while different to conventional all-digital solutions being able to deal with multiple different types of SI with minimal configuration overhead.

A low-power transmitter is proposed that applies edge-combining not only for frequency multiplication but also for quadrature signal generation. A phase-selection modulator uses the quadrature signals for frequency modulation, where frequency-shift keying is emulated by switching the quadrature signals according to the desired frequency deviation. Additionally, the selection modulator can interpolate eight auxiliary phases that enhance the spectral performance of the frequency modulation. The transmitter was fabricated in a 180 nm CMOS process. The target radio frequency in the 868 MHz ISM band is generated using an efficient switched-mode edge-combining power amplifier with a drain efficiency of 24%, while the transmitter operates at a frequency of 217 MHz to reduce power consumption. This transmitter works without external components and achieves a high overall power efficiency of 5 % with an RF output power of -7 dBm and a transmitter power consumption of 3.9 mW in an area of 0.94 mm2.

This work presents a 1.6 GHz to 2 GHz integer PLL with 2 MHz stepping, which is optimized for driving low-power 180 nm switched-capacitor (SC) circuits at a 1.2 V supply. To reduce the overall power consumption, a class-F VCO is implemented. Due to enriched odd harmonics of the oscillator, a rectangular oscillator signal is generated, which allows omitting output buffering stages. The rectangular signal results in a lowered power consumption and enables to directly drive SC-filters and an RF-divider using the oscillator signal. In addition, the proposed RF-divider includes a differential 4-phase signal generation at 868 MHz and 915 MHz SRD band frequencies that can be used for complex modulation schemes. With a fully integrated loop-filter, a maximum of integration is achieved. A test-chip was manufactured in a 1P6M 180 nm CMOS technology with triple-well option and confirms a PLL with a total active power consumption of 4.1 mW. It achieves a phase noise of -111 dBc/Hz at 1 MHz offset and a -42 dBc spurious response from a 1 MHz reference.

We present a family of hybrid structures, which combine subthreshold MOS operation with a single bipolar transistor. In contrast to typical BJT-based circuits, the PTAT voltage is generated from an asymmetric differential pair in weak inversion, and only the CTAT part depends on the parasitic PNP. A common feature is the signal generation and processing within a single feedback loop, which yields specifically simple solutions, with enhanced robustness towards supply and device variations. The bandgap reference, realized in 14/16nm FinFET, provides a 600mV output and > 60dB PSRR, at sub-1V power supply. We further present temperature sensors in 28nm CMOS and 14/16nm FinFET, which feature very low complexity and power. The first sensor includes a SAR ADC and achieves a precision of ± 3 °C after a 1-point trim under production conditions. The FinFE T sensor variant is a scaling-friendly solution, providing enhanced resolution with a duty-cycle modulated output.

A bi-directional active resistor structure with quasifloating gate MOS transistors and non-linearity compensation is used in a resistive negative feedback wide-band LNA implementation enabling a continuously tunable gain from 0dB to 24dB. The LNA has been realized in 65nm CMOS with a minimum noise figure of 2.5dB and IIP3 of -8dBm at highest gain. The LNA bandwidth is from 100MHz to 2GHz, with a power consumption of 12mW and an active area of 0.0375mm2.