In this paper, we propose a reliability-enhanced offset-canceling current sampling sense amplifier (REOCCS-SA) with a clamp voltage trimming technique to improve uniformity and uniqueness in spin-transfer-torque magnetic random-access memory (STT-MRAM)-based physically unclonable function (PUF). REOCCS-SA retains the structure of the OCCS-SA while incorporating a preliminary voltage amplification phase to enhance offset tolerance, thereby improving uniformity and uniqueness. Additionally, the clamp voltage trimming technique utilizes a resistor ladder to precisely adjust the clamp voltage, optimizing the reference current to achieve ideal uniformity. HSPICE simulations based on a 28 nm technology model show that the proposed REOCCS-SA reduces the standard deviation of uniformity by 75% and improves inter-Hamming distance (inter-HD) by 50% compared to the OCCS-SA. In addition, compared to other circuits proposed within the past decade, it achieves the lowest figure of merit, demonstrating the highest overall efficiency when operating as an STT-MRAM-based PUF. Furthermore, by applying theV${}_{\mathbf {CMP\_R}}$trimming and the automatic write-back technique, the PUF system using REOCCS-SA exhibits 49.95% uniformity, 50.83% inter-HD, and 0% intra-Hamming distance, confirming its overall robustness and stability.

Spin-orbit torque magnetic random access memory (SOT-MRAM) is a strong candidate to replace static RAM and dynamic RAM due to its high speed, near-zero standby power, and high density. Moreover, employing multi-level cell (MLC) techniques can further increase storage density. However, there are several challenges when sensing MLC: 1) The sensing margin is too small. 2) Three references and several different sensing are required to distinguish four states. As a result, significant read yield degradation, area overhead, and performance penalty are unavoidable. There are two conceptual methods for sensing MLC. The one-step parallel sensing scheme (SS) allows for data reading at once, but suffers from low read yield due to the offset of sensing circuit. On the other hand, the two-step SS using offset-cancellation technique can achieve a higher read yield but requires twice the time. To address these challenges, the single-reference-based MLC-SS using offset-cancellation technique is proposed. HSPICE simulation results, based on industry-compatible 28 nm model parameters demonstrate that the proposed MLC-SS can achieve a comparable read yield of 94.19% compared to 86.17% for the one-step parallel SS and 96.77% for the two-step SS, while requiring only one reference and incurring just a 20% increase in sensing time.

The current-latched sense amplifier (CLSA) is a promising candidate for detecting stored values in a memory cell. With technology shrinks, however, the input referred offset voltage ($V_{\mathrm{OS}})$in the SA increases, resulting in a degradation of the memory read yield. To obtain a high read yield,$V_{\mathrm{OS}}$reduction and cancellation techniques have become essential in deep-submicrometer technology nodes. When determining the$V_{\mathrm{OS}}$in the CLSA, the voltage mismatch of the input NMOS pair is the dominant factor ($\sim$75%), followed by that of the latch NMOS pair ($\sim$25%). In this paper, 1) slow rise time ($T_{\mathrm{RISE}})$control technique of SA enable signal and 2) reference voltage ($V_{\mathrm{REF}})$biasing technique are proposed, and the effectiveness of the proposed techniques are analyzed for the conventional CLSA with footswitch (FS-CLSA) and offset-canceling CLSA (OC-CLSA). Post-layout based HSPICE simulation results using 28 nm model parameters show that the FS-CLSA with size-up strategy (OC-CLSA) achieves a 17.7% (10.5%) reduction of the standard deviation of$V_{\mathrm{OS}}$($\sigma _{\mathrm{OS}})$when a slow$T_{\mathrm{RISE}}$of 0.6 ns is employed. The measurement results from a 28 nm test chip show that the OC-CLSA with$V_{\mathrm{REF}}$biasing achieves a 22% reduction of$\sigma_{\mathrm{OS}}$compared to the conventional OC-CLSA.

Most Internet of Things (IoT) devices demand a long battery life for mobility. Between the standby and active modes, the battery lifetime is the most optimal in the standby mode because IoT devices spend most of their lifetime in this mode. The nonvolatile flip-flop (NVFF) permits the total termination of the power supply during the standby mode. Recently, spin-transfer-torque magnetic-tunnel-junction (STT-MTJ)-based NVFF designs have been widely studied for enabling zero standby power consumption. Existing designs of the STT-MTJ-based NVFF have succeeded in achieving a target restore yield of$4\sigma $in the upper threshold of the voltage region (e.g., 0.6 V). However, when the supply voltage is lowered further with the intent to reduce the overall power consumption, the restore yield degrades because of increased process variations and offset voltages. This study proposes and analyzes four different STT-MTJ-based NVFF designs capable of operating in the subthreshold voltage region (e.g., 0.4 V). Monte Carlo simulation results based on industry-compatible 28-nm model parameters reveal that pMOS body biasing, one among the four proposed NVFF designs, achieves the target restore yield in the subthreshold voltage region with a reasonable transistor scale-up strategy, whereas the previous designs failed to restore saved data in the MTJ.

In the design of nonvolatile memory (NVM), the sensing scheme (SS) has become a read-energy bottleneck because the required read-cell current is too large to satisfy a target read yield. This problem is further aggravated by technology scaling because increased process variation and reduced supply voltage (VDD) require more current to satisfy the target read yield. This paper proposes an offset-canceling single-ended SS (OCSE-SS) with one-bit-line precharge architecture (1BLPA) that is intended for use in ultralow power NVM applications. The test chip is fabricated using 65-nm process technology, and the measurement results show that the read energy per bit of the OCSE-SS is 1/3 compared to that of the conventional SS (Conv-SS). The read energy reduction comes from the singleended sensing, offset cancellation, and 1BLPA features. Moreover, when a resistance difference between the data and reference cells is as small as 0.5 kQ, the OCSE-SS reads successfully with a VDD of 1.0 V and a sensing time (tSEN) of 17 ns due to the offset cancellation characteristic, whereas the Conv-SS fails regardless of VDD and tSEN values.

As the technology node scales down, a sufficient read current that is capable of achieving a target read yield cannot be used because of the read disturbance problem in spin-transfer-torque random access memory (STT-RAM). As an alternative method, increasing the sensing circuit (SC) area is generally considered because it can reduce the threshold voltage (Vth) variations. However, the increased SC area can adversely reduce the read yield due to the increased load capacitance. The effects of the increased area on read yield can be different according to the SCs because of their own characteristics. In this work, the trends of read yield according to the area are analyzed for two representative SCs, and the areas of two SCs are optimally designed to have high read yield.

As the technology node scales down, the spin-transfer-torque random access memory (STT-RAM) has been considered as a promising memory solution owing to its scalability. However, the increased process variation and the reduced supply voltage lead to degradation in the sensing yield (SY) as well as an increase in the read disturbance probability. Temperature variation further aggravates this phenomenon. Thus, achieving a target SY with a lower sensing current in all process, voltage, and temperature (PVT) corners has become an important issue in a deep-submicrometer technology node. In this paper, we propose a corner-aware dynamic gate voltage scheme to achieve constant-current sensing, regardless of the PVT variations. By adopting this scheme, the state-of-the-art sensing circuits (SCs) can significantly reduce the sensing current, while achieving the target read yield. The Monte Carlo HSPICE simulation results using industry-compatible 45-nm model parameters show that the offset-canceling dual-stage SC that uses the proposed scheme satisfies a target SY of six-sigma (96.34% for 32 Mb) with two times lower sensing current and two times lower read energy compared with that using a fixed gate voltage.

Spin-transfer-torque random access memory (STT-RAM) has attracted much research interest because of its characteristics of nonvolatility (i.e., zero standby power) and small cell size (i.e., high density and high performance). As the technology node is scaled down, however, the sensing margin of the STT-RAM is degraded because of the increased process variation and reduced supply voltage. To improve the sensing margin, this brief focuses on a reference scheme design capable of reducing the reference resistance distribution. A multiple-cell reference (MCR) scheme is proposed that achieves the narrow reference resistance distribution. Moreover, the MCR scheme does not exhibit parasitic mismatch, regularity problem, read disturbance, and write current degradation, and it also has small area overhead.

Due to the increased process variation and reduced supply voltage in deep submicrometer technology nodes, an offset-tolerant sensing scheme has become essential. However, most offset-tolerant sensing schemes suffer from inherent performance degradation owing to multiple-stage sensing. In this paper, a dual Vrefsensing scheme (DVSS) that selectively uses an optimal Vrefbetween Vref+and Vref-is proposed. This scheme is tolerant to process variations, and can be used as a spin-transfer-torque random access memory. Because of no additional sensing stage, the offset-tolerant sensing is achieved without sacrificing the performance. The optimal Vrefis selected after fabrication, and the calibrated switch control bit, which contains Vrefselection information, is stored permanently in an on-chip nonvolatile latch. Monte Carlo HSPICE simulation results, using an industry-compatible 45-nm model parameters, show that the proposed DVSS achieves a read yield of 98.24% for 32 Mb (6.1 sigma) with 2× faster sensing speed and 1.5× lower read energy per bit compared with the state-of-the-art offset-tolerant sensing scheme.

A global reference-circuit (RC), which means one RC is shared with many sensing circuits (SC), is being considered for high-bandwidth STT-RAMs because of the low power consumption and small area characteristic. However, using the global RC for high-bandwidth STT-RAMs causes a droop effect and coupling noise effect, leading to the significant performance degradation. Thus, the validity of using the global RC should be identified. In this paper, the local RC and various global RCs are introduced, and compared in aspects of area, sensing time, and power consumption. By classification of the merits and demerits of various RCs, we present the following requirements of proper RC for high-bandwidth STT-RAMs: 1) small area, 2) no performance degradation, 3) low power consumption, and 4) process variation tolerant reference signal generation.

In this paper, a novel magnetic tunnel junction (MTJ) based non-volatile flip-flop (NVFF) is proposed. The separated latch and sensing circuit structure maximizes the performance of latch operation, minimizes power consumption, and improves MTJ lifetime. Furthermore, the merged sensing and write circuit structure reduces area overhead. HSPICE simulation results using a 45-nm technology model show that the proposed NVFF achieves three times smaller power delay product with a 2% smaller layout area than the conventional NVFF.

Spin-transfer torque random access memory (STT-RAM) is considered to be a leading candidate for next-generation memory. As technology scales, however, the sensing margin of STT-RAM is significantly degraded because of increased process variation. Furthermore, the sensing current should be <;20 μA to protect the read disturbance in the beyond 45-nm technology, leading to a further decrease in the sensing margin. To achieve a target yield of six sigma in the beyond 45-nm technology with a sensing current of <;20 μA, an offset-canceling triple-stage (OCTS) sensing circuit is proposed in this brief. The OCTS sensing circuit can overcome the sensing margin and read disturbance problems by sacrificing the sensing time. Monte Carlo HSPICE simulation results using a 45-nm technology model show that the OCTS sensing circuit achieves a target yield of six sigma (96.74% for 32 Mb) with a sensing current of 20 μA and a sensing time of 6.4 ns.

When the input voltage difference of a sense amplifier (SA) exceeds the offset voltage (VOS), the SA correctly detects it and outputs a large signal. However, when the input voltage is in a certain region, the SA can fail to sense the input voltage difference even if it is sufficiently large. This input voltage region is defined as the sensing dead zone of the SA. Because sensing dead zones differ depending on SAs and the input voltages to the SA differ depending on the memory devices, analyzing the sensing dead zone is very important. In this brief, we analyze the sensing dead zones of the most popular latch-type SAs: voltage- and current-latched SAs. Furthermore, a suitable latch-type SA scheme is suggested for various SA input voltages in terms of sensing delay, power consumption, and PDP, using a 65-nm predictive technology model at a VDD of 1.1 V.

In this paper, we categorize STT-MTJ based non-volatile flip-flops (NV-FF) into two basic structures: merged latch and sensing circuit (MLS) structure and separated latch and sensing circuit (SLS) structure. We also analyze the two structures with various types of sensing and write circuits. HSPICE simulation results using the industry-compatible 45-nm model parameter shows the SLS structure has better performance according to D-Q delay, PDP, and sensing current than the MLS structure because the SLS structure can optimize the FF operation and the sensing operation independently. Among various types of sensing circuit, the cross coupled inverter based sensing circuit including two MTJs and the single ended sensing circuit including two MTJs show better performances on low sensing current and high yield.