This paper presents a novel Dynamic-Window (DW) Digital-to-Analog Converter (DAC) switching technique to enhance the power efficiency of the Successive Approximation Register (SAR) Analog-to-Digital Converter (ADC). DW is achieved by dynamically adjusting the reference voltage used by the DAC when the input signal amplitude falls within a certain pre-specified window. The proposed DW is implemented by choosing combinations of DAC slices to effectively create an attenuation of the reference voltage thus dynamically adjusting the SAR ADC’s successive approximation window. This method monitors the input signal amplitude using a coarse front-end (FE) circuit that can be easily implemented with negligibly small energy overhead. DW is particularly energy-efficient for real-world signals with a high Peak-to-Average Ratio (PAR) such as audio and OFDM signals in wireless communication. The effects of DW on a 12-bit 1MS/s SAR ADC are simulated in MATLAB®for a Gaussian distributed input signal with a 6σ, 8σ input full-scale (FS) range, demonstrating its ability to reduce DAC energy consumption respectively by 35%, 41% with 2-level DW and 45%, 54% with 4-level DW. The simulations also explore the effects of DW in the ADC performance metrics such as Signal-to-Noise and Distortion Ratio (SNDR), Differential Non-Linearity (DNL), and Integral Non-Linearity (INL) to show DW can be implemented without major degradation in ADC performance for DAC capacitor mismatch as high as 2.5% per fF.

This paper describes the design and implementation of a 4 MHz bandwidth$3{^{\text {rd}}}$-order Discrete-Time (DT) Passive Delta-Sigma Modulator (${\mathrm {P\Delta\Sigma M}}$), which avoids the use of supply voltage-sensitive linear amplifiers. The Switched-Capacitor (SC) operation and amplifier-less nature of its loop filter render the proposed modulator highly supply voltage- and clock frequency-flexible. To explain our design choices, we investigate two key design challenges unique to${\mathrm {P\Delta\Sigma M}}$s. Firstly, the noise criticality of the quantizer ADC due to the lack of (voltage) gain in the loop filter preceding it. Secondly, the inaccessibility of the readily synthesizable and highly frequency-selective loop filter frequency responses typically employed in${\mathrm {\Delta\Sigma M}}$s, caused by the absence of linear amplifiers. We show that the noise-power trade-off of the quantizer ADC in 1 bit P$\Delta \Sigma $Ms is the same as that of the first integrator amplifier in Active${\mathrm {\Delta\Sigma M}}$. Next, we cover the suitability of several passive filters for use in${\mathrm {P\Delta\Sigma M}}$loops. This leads to the selection of the voltage-sampled Charge-Rotating IIR (CR-IIR) filter, for which we show${\mathrm {\Delta\Sigma M}}$-oriented design equations, on which we base the design of our$3{^{\text {rd}}}$-order DT${\mathrm {P\Delta\Sigma M}}$. Measurement results on the resulting prototype${\mathrm {P\Delta\Sigma M}}$, implemented in GlobalFoundries 22 nm FD-SOI CMOS, demonstrate that it achieves a 71.9 dB peak SNDR and 4 MHz bandwidth while consuming 4.4 mW from a 0.9 V supply and occupying 0.076 mm$^{\mathrm {\mathbf {2}}}$of silicon area. The prototype${\mathrm {P\Delta\Sigma M}}$continues to operate at a$2.25\times $reduced supply voltage of 0.4 V, albeit at a reduced bandwidth of 156.25 kHz, where it achieves a peak SNDR of 62 dB while consuming 37.8$\mu $W.

A novel algorithm is presented that can resolve frequency ambiguity that arises from sampling a set of signals spanning more than a single Nyquist zone. The method uses two samplers, each sampling the same input signal with different (non-integer multiple) sampling rates. The algorithm is able to resolve frequency ambiguity and reconstruct signals with an orthogonal frequency basis spanning multiple Nyquist zones, provided that the aggregate information-bearing bandwidth of the signals is less than half the cumulative data converter sampling rates. This manuscript describes the theoretical background for the algorithm and validates it through measurements performed on a test-board comprising of two 10 bit analog-to-digital converters clocked at two different (non-integer multiple) sample rates. Measurements show that even in the presence of aliasing, an orthogonal signal spanning multiple Nyquist zones can be fully reconstructed.

A clock and data recovery (CDR) module in 90nm CMOS, for a 10Gbps serial link, integrated with a -18dB attenuation channel, is presented. A novel dual-loop CDR with separate charge pumps for high-gain frequency acquisition, and low-gain phase tracking has been introduced. The CDR utilizes a full rate architecture with a single VCO along with a selection logic for switching to the desired charge pump, resulting in a 4.2mW power consumption from the VCO. A current-steering charge pump with DCVSL inputs reduced the glitches in the up and down currents thereby reducing the ripples on the control voltage to 1mV in the locked condition. An rms and peak periodic jitter of 0.382ps and 0.759ps respectively were achieved with a PRBS sequence of 27bits, resulting in a design compliant with SONET OC-192 specifications.