Spatial computing has become a cornerstone of consumer electronics in the metaverse era, powering augmented reality (AR), virtual reality (VR) head-mounted displays (HMDs), and smart glasses. A key enabling technology for these mobile platforms is visual odometry (VO), which supports accurate motion tracking for seamless navigation and interaction. However, deploying deep learning-based VO on resource-constrained edge devices remains challenging due to high computational complexity, memory usage, and power demands. Moreover, critical operations such as feature matching, triangulation, and nonlinear optimization are notoriously intensive for embedded processors, underscoring the need for application-specific acceleration. This work presents a hardware-algorithm co-designed VO acceleration system for edge deployment, implemented on a Xilinx UltraScale+ MPSoC ZCU104. The system integrates an ARM Cortex-A53 processor, a neural network accelerator, and custom modules for feature matching and pose refinement. With hardware-aware algorithmic optimizations, the proposed design achieves a 255.6× speedup in neural inference, 13.7× acceleration for geometric modules, and an additional 2.1× gain through task-level parallelism, sustaining 30.6 FPS in real time. Compared to existing FPGA-based VO designs, our system offers the highest localization accuracy while maintaining real-time performance, demonstrating its practical viability for spatial computing in real-world scenarios.

Recent advancements in spatial computing have transformed the interaction paradigm between digital information and physical environments, enabling context-aware applications that enhance daily activities across healthcare, education, entertainment, and industry. At the heart of spatial computing lies visual odometry (VO), which estimates real-time device motion to accurately align virtual content with the real world. However, achieving real-time RGB-D VO on mobile and wearable platforms remains challenging due to limited computing resources, particularly stringent memory constraints. In this article, we present a memory-efficient RGB-D VO accelerator developed via algorithm–hardware codesign. Our method significantly reduces memory consumption by employing a hybrid pipeline that integrates sparse, feature-based initialization with dense, direct-based optimization, thereby eliminating memory-intensive image pyramids. To the best of our knowledge, this is the first pyramid-free RGB-D VO accelerator that achieves real-time operation with only 128 kB of on-chip SRAM, demonstrating the effectiveness of algorithm–hardware codesign in memory-constrained environments. Implemented in TSMC 40-nm CMOS technology, the proposed architecture achieves a 32.78% reduction in memory usage, a 10.20% smaller chip area, and a$1.68\times $improvement in frame rate compared to baseline designs, efficiently processing RGB-D data at 34.4 f/s using only 128 kB of on-chip memory.

The spatial computing has been a popular topic in recent years, driving the development and use of consumer electronics such as AR/VR head-mounted displays (HMDs) and smart glasses. A critical component of these mobile devices is visual odometry (VO), which provides on-device motion tracking to allow users to interact with and move freely in virtual space. VO must be sufficiently efficient to handle real-time processing on resource-constrained mobile devices. To meet this requirement, we propose a memory-efficient algorithm from a hardware perspective, achieving over tenfold memory savings. Our architecture further reduces memory usage by 32.78%, area by 10.20%, and improves performance by 1.68x. Implemented in TSMC 40 nm technology, it demonstrates competitive results compared to other works, handling nearly three times more data due to processing the depth map.

Augmented Reality (AR) and Mixed Reality (MR) have gained more and more awareness among consumers in recent years. However, pose accuracy, stability, and latency still left a lot to be desired when it comes to users’ experiences and acceptance. This work focuses on marker-based rigid object pose accuracy and computation latency. We developed a flexible marker-based accurate rigid object 6-DoF pose tracking system. First, a calibration algorithm for marker pose configuration is proposed after the multiple-marker system is setup for a target application. Next, a pose tracking system is developed to achieve sub-mm performance with the calibrated marker pose configuration. Moreover, a high-throughput pose engine hardware accelerator is proposed to achieve real-time performance.

In recent years, the metaverse has been a popular topic, and it drives many consumer electronics like AR/VR HMDs (Head Mounted Displays) and smart glasses. In these mobile devices, a critical technology is visual odometry (VO), which provides on-device motion tracking so that the user can interact with and move freely in the virtual information. In this work, we propose a novel hybrid monocular visual odometry framework named DPDM (Deep Pose and Deep Match), which properly integrates deep learning into geometry-based methods. We revisit the traditional feature-based optimization and improve it by replacing its crucial components with deep prediction. With the powerful high-level information extraction ability of deep neural networks, DPDM can obtain robust and accurate results through a simple frame-to-frame sparse feature-based pose refinement module. Experiments show that DPDM can outperform traditional VO and pure learning-based VO. Compared to state-of-the-art hybrid VO, DPDM can achieve competitive performance and higher FPS (Frames Per Second).

Different from the ordinary apparatus and plug-in devices on bikes, this research brings up a novel system called SaFePlay+, Smart Footwear Platform Plus. The system includes a pair of knee motion sensing module and smart pressure and motion sensing insole, analyzed module and interactive App. SaFePlay+ can immediately collect lower limbs information of users. Moreover, through the novel algorithm of wearable power analyzer, it can help users to understand their body condition in order to adjust the posture, raise the efficiency and avoid sports injury. Through the verification of the apparatus, it shows that our method can get good cadence and power performance.

Office workers usually have problems of back and neck pain because of their bad posture which they always keep. In order to solve the problems, we design a smart suit, Heath Posture Protector (HP2), and 4 serious games for rehabilitation. Besides, we use machine learning to train the motion model and apply the model in playing the serious games. We expect the user who wears the smart suit HP2 can easily play the serious games, and furthermore, they can stretch the muscles of upper body by the guidance in games to reduce or even prevent the problems of upper-body pains.

In this paper, a memory-efficient and low-complexity architecture is proposed for the scalable video encoder, achieving the requirement of the multi-source digital home environment. The proposed very-large-scale integration architecture of the scalable video encoder is implemented in TSMC 0.18-μm 1P6M CMOS technology. The proposed hardware is synthesized under 0.18-μm CMOS technology; resulting throughput is 93.3M samples/sec, occupying 182K gates. Resulting power dissipation is 42.13 mW, operating at 150 MHz clock source. The performance of proposed work (the throughput) meets 1080p@30 fps real-time encoding, constrained by wireless high definition video interface for mobile environment.