Parameter tuning for multi-FPGA partitioning algorithms represents a bottleneck in modern chip emulation and verification workflows. Current multilevel partitioning tools require manual configuration of various parameters, where each evaluation can take tens of seconds to minutes, making exhaustive search impractical and expert-driven tuning both time-consuming and suboptimal. To automate this process, we propose a preference-guided Bayesian optimization framework specifically designed for industrial FPGA partitioning parameter tuning under limited evaluation budgets. Our approach maximizes the minimum timing slack by incorporating domain-specific insights: we exploit the strong correlation between cutsize and timing performance through a priority-based ranking scheme that guides a pairwise Gaussian process to learn configuration preferences. Additionally, we introduce a kernel input transformation that properly handles the mixed discrete-continuous parameter space typical in EDA tools. Our method converges faster with fewer evaluations and achieves the best timing slack in 60–70% of cases on industrial circuit benchmarks compared to existing methods including standard Bayesian optimization, quasi-random sampling, and state-of-the-art preference learning techniques. The proposed framework reduces parameter tuning from days of manual effort to hours of automated optimization, offering practitioners a deployment-ready solution that improves both design quality and engineering productivity.

Power distribution network (PDN) optimization in 2.5-D chiplet architectures represents a critical bottleneck as designs scale to 100+ integrated chiplets, where decoupling capacitor placement becomes a multi-port optimization challenge requiring millions of expensive electromagnetic (EM) simulations. Current state-of-the-art (SOTA) methods - from genetic algorithms (GA) to reinforcement learning (RL) - treat PDN as black-box functions, failing to exploit inherent physical structure and scaling exponentially with problem complexity. We introduce Φ-BO, the first physics-informed Bayesian optimization (BO) framework specifically designed for multi-port decoupling capacitor placement in 2.5-D chiplet PDN. Our key innovation systematically integrates EM field theory into machine learning (ML) optimization through novel spatial feature transformations and Multi-Port Aware Transformation (MPAT), enabling a paradigm shift from black-box to physics-aware optimization. This approach captures spatial dependencies and port coupling effects, dramatically reducing effective problem dimensionality while enabling intelligent exploration of discrete placement configurations. Demonstrated on a 22-chiplet RISC-V processor design, Φ-BO achieves 23% impedance improvement, and 3 × faster convergence compared to SOTA methods.

In analog circuit design, transistor sizing remains a critical challenge due to high-dimensional parameter spaces and expensive simulations. While Bayesian optimization shows promise, existing methods struggle with the "curse of dimensionality." Inspired by expert designers’ workflow of focusing on key parameters first before gradually optimizing secondary parameters, we introduce DIVE (Dynamic Information-guided Variable Expansion), a framework that reformulates parameter optimization as an information efficiency maximization problem. Unlike approaches that explore all parameters simultaneously, DIVE progressively includes design variables with the highest information content. Our framework introduces three innovations: (1) constraint-aware weighted mutual information analysis that evaluates parameters’ contributions to objectives and constraints; (2) an adaptive variable inclusion mechanism that determines when to expand the optimization space; and (3) a mutual information-guided kernel learning strategy for Gaussian process models. Evaluations across multiple analog circuits demonstrate that DIVE achieves a 1.61×-21.11× reduction in required simulations while delivering up to 2.69× spec improvements over the state-of-the-art methods. By progressing from simple to complex parameter spaces based on information theory, DIVE establishes a new paradigm for reaching deeper optima by mimicking experienced designers’ design philosophy in circuit optimization. Our code is available1.

Advancing technology nodes have significantly increased the complexity of transistor sizing in analog circuit design. Although artificial intelligence (AI) techniques show potential, their lack of integrated domain expertise often leads to slow convergence in practical applications. We propose ASTRA (Automatic Sizing of Transistors with Reasoning Agents), a novel optimization framework that implements the Model Context Protocol (MCP) to create structured reasoning pathways between Large Language Models (LLMs), domain knowledge bases, and Bayesian Optimization (BO). ASTRA introduces a two-stage process: first, MCP-guided design initialization that leverages Retrieval-Augmented Generation (RAG) to quickly identify feasible regions using gm/ID methodology; and second, BO-based optimization focused on critical transistors, identified through LLM reasoning with data-driven validation. A key innovation of ASTRA is its ability to seamlessly integrate with and enhance virtually any existing transistor sizing algorithm at minimal additional cost. Unlike purely data-driven or black-box LLM approaches, ASTRA maintains traceable decision processes that can be verified and refined. Evaluated on three real-world analog circuits, ASTRA enhances multiple classical optimization methods, achieving up to 4.35× fewer simulation iterations and 2.36× performance improvements, demonstrating its effectiveness as a general open-source framework for advancing analog circuit sizing.1

Static Random-Access Memory (SRAM) yield analysis is essential for semiconductor innovation, yet research progress faces a critical challenge: the large gap between simplified academic models and the complexities observed in practice. The lack of open, higher-fidelity benchmarks has hindered reproducibility and transferability, as promising academic techniques often fail to carry over to more realistic settings. We present OpenYield, an open-source ecosystem that aims to narrow this gap through three contributions: (i) An SRAM circuit generator that explicitly incorporates second-order effects (interconnect/line parasitics, inter-cell leakage coupling, and peripheralcircuit variations) that are commonly omitted in academic studies. (ii) A standardized evaluation platform with a simple interface and baseline yield-analysis implementations to enable fair comparisons and reproducible research on these higherfidelity circuits. (iii) An optimization platform for transistor-level sizing under these models, supporting reproducible studies of robustness/efficiency trade-offs. OpenYield aims to foster more reproducible and transferable progress in SRAM-yield research. The framework is publicly available at OpenYield:URL.

Automatic transistor sizing in circuit design continues to be a formidable challenge. Despite that Bayesian optimization (BO) has achieved significant success, it is circuit-specific, limiting the accumulation and transfer of design knowledge for broader applications. This paper proposes (1) efficient automatic kernel construction, (2) the first transfer learning across different circuits and technology nodes for BO, and (3) a selective transfer learning scheme to ensure only useful knowledge is utilized. These three novel components are integrated into BO with Multi-objective Acquisition Ensemble (MACE) to form Knowledge Alignment and Transfer Optimization (KATO) to deliver state-of-the-art performance: up to 2x simulation reduction and 1.2x design improvement over the baselines.

Abstract The creativity of an excellent design work generally comes from the inspiration and innovation of its main visual features. The similarity among primary visual elements stands as a paramount indicator when it comes to identifying plagiarism in design concepts. This factor carries immense importance, especially in safeguarding cultural heritage and upholding copyright protection. This paper aims to develop an efficient similarity evaluation scheme for graphic design. A novel deep visual saliency feature extraction generative adversarial network is proposed to deal with the problem of lack of training examples. It consists of two networks: One predicts a visual saliency feature map from an input image and the other takes the output of the first to distinguish whether a visual saliency feature map is a predicted one or ground truth. Unlike traditional saliency generative adversarial networks, a residual refinement module is connected after the encoding and decoding network. Design importance maps generated by professional designers are used to guide the network training. A saliency-based segmentation method is developed to locate the optimal layout regions and notice insignificant regions. Priorities are then assigned to different visual elements. Experimental results show the proposed model obtains state-of-the-art performance among various similarity measurement methods.

Privacy and efficiency are two important but seemingly contradictory objectives in radio‐frequency identification (RFID) systems. On one hand, RFID aims to identify objects easily and quickly, on the other hand, users want to maintain the necessary privacy without being tracked down for where they are and what they are doing. Common RFID privacy‐preserving authentication protocols can be classified into tree‐based schemes and group‐based schemes, and all these schemes do not meet the dual goals of efficiency and security at the same time. In 2013, Sakai et al . proposed a randomised skip lists‐based authentication protocol (RSLA), and claimed that the RSLA can resist compromise attacks. In this study, the authors analyse the compromise attacks on RSLA and show that there is no obvious advantage with respect to the privacy of the RSLA compared with balanced tree‐based schemes. Moreover, it is reasonable to claim that protocols based on skip lists are also vulnerable to compromise attacks.

With the development of cloud computing and mobility, mobile cloud computing has emerged and become a focus of research. By the means of on-demand self-service and extendibility, it can offer the infrastructure, platform, and software services in a cloud to mobile users through the mobile network. Security and privacy are the key issues for mobile cloud computing applications, and still face some enormous challenges. In order to facilitate this emerging domain, we firstly in brief review the advantages and system model of mobile cloud computing, and then pay attention to the security and privacy in the mobile cloud computing. By deeply analyzing the security and privacy issues from three aspects: mobile terminal, mobile network and cloud, we give the current security and privacy approaches.