Demo Data from EDBT 2026 / reviewers in the wild / expert
Frederick F. Sellers Jr.
dblp:133/9762
· DBLP profile ↗
5ranked-venue papers
4as first author
0since 2021 · last 1969
—ORCID · none
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 3 · 2 first-authorTheory of computation · 2 · 2 first-author
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
2 papers |
Electronic design automation · 73% Processor architecture and microarchitecture · 12% Integrated circuit design · 12% | |
| Theoretical computer science
1 paper |
Coding theory · 100% |
Topics — the 8 heaviest of 8, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Electronic design automation › hardware verification and test › test generation
boolean difference |
0.0 | 1 | 1968 | Analyzing Errors with the Boolean Difference · IEEE Trans. Computers 1968 |
Electronic design automation › hardware verification and test
fault analysis |
0.0 | 1 | 1968 | Analyzing Errors with the Boolean Difference · IEEE Trans. Computers 1968 |
Electronic design automation
hardware verification and test |
0.0 | 1 | 1968 | Analyzing Errors with the Boolean Difference · IEEE Trans. Computers 1968 |
Integrated circuit design › digital circuit design › arithmetic circuit design
adder design |
0.0 | 1 | 1963 | The Carry-Dependent Sum Adder · IEEE Trans. Electron. Comput. 1963 |
Processor architecture and microarchitecture › arithmetic unit
arithmetic unit design |
0.0 | 1 | 1963 | The Carry-Dependent Sum Adder · IEEE Trans. Electron. Comput. 1963 |
Coding theory
error-correcting codes |
0.0 | 1 | 1962 | Bit loss and gain correction code · IRE Trans. Inf. Theory 1962 |
Electronic design automation › hardware verification and test
fault detection |
0.0 | 1 | 1963 | The Carry-Dependent Sum Adder · IEEE Trans. Electron. Comput. 1963 |
Hardware reliability and fault tolerance › error detection
parity prediction |
0.0 | 1 | 1963 | The Carry-Dependent Sum Adder · IEEE Trans. Electron. Comput. 1963 |
Methods — techniques the papers use, named apart from their topics
parity prediction · 0.0carry-dependent sum · 0.0boolean difference · 0.0
| Year | Publication | Venue | Position |
|---|---|---|---|
| 1969 | Correction to "Analyzing Errors with the Boolean Difference"1
Frederick F. Sellers Jr., Mu Yue Hsiao, LeRoy W. Bearnson |
IEEE Trans. Computers | 1 |
| 1968 | Analyzing Errors with the Boolean DifferenceabstractAbstract—The Boolean difference is defined. It is shown through example how the Boolean difference is used to analyze the effect of errors on the outputs of logic circuits. Examples are given of error detection problems, analysis of redundant logic, and the generation of diagnostic sequences. Frederick F. Sellers Jr., Mu Yue Hsiao, LeRoy W. Bearnson |
IEEE Trans. Computers | 1 |
| 1963 | The Carry-Dependent Sum AdderabstractThe correct operation of addition in a digital computer is very important. In this paper, the authors exhibit a checking scheme called ``carry-dependent sum add'' which is based on the parity prediction method. This scheme assures single-fault detection without duplication of the carry circuit. An example of a binary adder and a decimal adder using this scheme are included. Mu Yue Hsiao, Frederick F. Sellers Jr. |
IEEE Trans. Electron. Comput. | 2 |
| 1962 | Bit loss and gain correction codeabstractA block code is presented that will correct an error consisting of the gain or loss of a bit (binary digit) within the block. The code can be generalized to correct the loss or gain of a burst of bits. A further feature is the possibility of correcting additive errors appearing in the vicinity of the bit loss or gain. An additive error is a bit changed from 0 to 1 or from 1 to 0. The code is constructed by inserting a known character into a burst-error-correcting code at periodic intervals. The known character locates the approximate position of the bit loss or gain. At the location a bit is inserted or removed from the block, depending on whether a loss or a gain has occurred. The error-correcting code then corrects the erroneous bits between where the error occurred and where the correction took place. Frederick F. Sellers Jr. |
IRE Trans. Inf. Theory | 1 |
| 1961 | On 'Upper bounds for error-detecting and correcting codes of finite length' by Wax, N
Frederick F. Sellers Jr. |
IRE Trans. Inf. Theory | 1 |