Howard L. Yudkin

dblp:134/3722 · DBLP profile ↗
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2ranked-venue papers
1as first author
0since 2021 · last 1967
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 1Theory of computation · 1 · 1 first-author

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Theoretical computer science
1 paper
Logic in computer science · 50% Automata and formal languages · 50%

Topics — the 2 heaviest of 2, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Automata and formal languages
finite automata
0.011966
On Nonlinear Binary Sequential Circuits and Their Inverses · IEEE Trans. Electron. Comput. 1966
Logic in computer science
sequential circuit theory
0.011966
On Nonlinear Binary Sequential Circuits and Their Inverses · IEEE Trans. Electron. Comput. 1966

Methods — techniques the papers use, named apart from their topics

z-transform · 0.0transfer function · 0.0response functions · 0.0
YearPublicationVenuePosition
1967 Review of 'Communication Systems and Techniques' (Schwartz, M., et al; 1966)
Howard L. Yudkin
IEEE Trans. Inf. Theory1
1966 On Nonlinear Binary Sequential Circuits and Their Inverses
abstract
This paper discusses single-input, single-output binary sequential circuits composed of adders, multipliers and delay units. The principal results are: 1) Finite feedforward circuits are characterized by a response function (rf) which permits the determination of the output for an arbitrary input. 2) Corresponding to every rf is a transfer function (tf) which is obtained by a multidimensional Z-transform of the rf. This tf permits the determination of the response of a feedforward circuit by transform domain techniques. 3) Every tf may be synthesized as a physical circuit. 4) A canonic form is defined for every tf. With this canonic form is identified an implementation which contains a minimum number of delay units and adders. 5) Nonfeedforward circuits are called well defined if they meet certain physically meaningful restrictions. 6) Well-defined circuits may be classified as those which have inverses (class I) and those which do not. Membership in class I is shown to be a property of circuits which established one-one maps of inputs onto outputs. Circuits which do not belong to class I have neither left nor right inverses. 7) An intimate connection between inverses and feedback circuits is established. It is shown that any well-defined feedback circuit and a related circuit in I are mutually inverse. 8) It is shown that the necessary and sufficient condition for a feedback circuit to be well defined is that the circuit in the feedback loop contains delay.
Barney Reiffen, Howard L. Yudkin
IEEE Trans. Electron. Comput.2