EDBT 2026 Demo / reviewers in the wild / expert
Albert C. L. Chiang
dblp:134/4422
· DBLP profile ↗
4ranked-venue papers
3as first author
0since 2021 · last 1972
—ORCID · none
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 3 · 2 first-authorTheory of computation · 1 · 1 first-author
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Theoretical computer science
4 papers |
Coding theory · 96% Information theory · 4% | |
| Computer architecture, parallel and distributed computing, and storage systems
2 papers |
Electronic design automation · 87% Hardware reliability and fault tolerance · 13% |
Topics — the 12 heaviest of 14, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Coding theory
error-correcting codes |
0.0 | 2 | 1972 | Notes on the Arithmetic BN Modulo A Codes · IEEE Trans. Computers 1972 Arithmetic norms and bounds of the arithmetic AN codes · IEEE Trans. Inf. Theory 1970 |
Electronic design automation › hardware verification and test › test generation
boolean difference |
0.0 | 1 | 1972 | Path Sensitization, Partial Boolean Difference, and Automated Fault Diagnosis · IEEE Trans. Computers 1972 |
Electronic design automation › hardware verification and test
fault detection |
0.0 | 1 | 1972 | Path Sensitization, Partial Boolean Difference, and Automated Fault Diagnosis · IEEE Trans. Computers 1972 |
Electronic design automation › hardware verification and test
fault diagnosis |
0.0 | 1 | 1972 | Path Sensitization, Partial Boolean Difference, and Automated Fault Diagnosis · IEEE Trans. Computers 1972 |
Electronic design automation
hardware verification and test |
0.0 | 1 | 1972 | Path Sensitization, Partial Boolean Difference, and Automated Fault Diagnosis · IEEE Trans. Computers 1972 |
Electronic design automation › hardware verification and test › test generation
path sensitization |
0.0 | 1 | 1972 | Path Sensitization, Partial Boolean Difference, and Automated Fault Diagnosis · IEEE Trans. Computers 1972 |
Coding theory › error-correcting codes
arithmetic codes |
0.0 | 1 | 1972 | Notes on the Arithmetic BN Modulo A Codes · IEEE Trans. Computers 1972 |
Coding theory › error-correcting codes › arithmetic codes
arithmetic error-correcting codes |
0.0 | 1 | 1970 | Arithmetic norms and bounds of the arithmetic AN codes · IEEE Trans. Inf. Theory 1970 |
Coding theory › error-correcting codes › arithmetic codes
AN codes |
0.0 | 1 | 1970 | Arithmetic norms and bounds of the arithmetic AN codes · IEEE Trans. Inf. Theory 1970 |
Coding theory › error-correcting codes › coding bounds
error-correcting code bounds |
0.0 | 1 | 1970 | Arithmetic norms and bounds of the arithmetic AN codes · IEEE Trans. Inf. Theory 1970 |
Coding theory › error-correcting codes
hamming codes |
0.0 | 1 | 1970 | Coding Techniques for Failure-Tolerant Counters · IEEE Trans. Computers 1970 |
Coding theory › error-correcting codes
reed-muller codes |
0.0 | 1 | 1970 | Coding Techniques for Failure-Tolerant Counters · IEEE Trans. Computers 1970 |
Methods — techniques the papers use, named apart from their topics
boolean difference analysis · 0.0number-theoretic construction · 0.0majority elements · 0.0majority element · 0.0error-correcting schemes · 0.0binary norm computation · 0.0
| Year | Publication | Venue | Position |
|---|---|---|---|
| 1972 | Notes on the Arithmetic BN Modulo A CodesabstractProperties of arithmetic norms of integers are applied to the study of arithmetic BN modulo A codes. Some new properties of such codes are established. Bounds on the size of such codes are derived and an efflcient algorithm for finding the optimal single and double error-correcting BN modulo A codes is developed. Albert C. L. Chiang, Irving S. Reed |
IEEE Trans. Computers | 1 |
| 1972 | Path Sensitization, Partial Boolean Difference, and Automated Fault DiagnosisabstractA tool employed in automated fault diagnosis is emphasized: path sensitization by partial Boolean difference analysis. Motivated by the analogy between a test system and a communication system, a model for fault detection of a logic net is outlined from the standpoint of information theory. The classical ``path sensitizing'' technique is made systematic using the partial Boolean difference. This technique is based on a new theorem on the partial Boolean difference. Finally, a programmable fault detection algorithm is presented along with an example. Albert C. L. Chiang, Irving S. Reed, Anthony V. Banes |
IEEE Trans. Computers | 1 |
| 1970 | Coding Techniques for Failure-Tolerant CountersabstractThis paper delineates an application of two classes of parity-check codes to the design for failure-tolerant counters. They are 1) a modified first-order Reed-Muller code and 2) the perfect Hamming code. The first code employs a majority element for implementing the error-correcting scheme while the second one makes use of a variable 2j-2+1-out-of-2j-1+1 majority element. These coding techniques can be applied in principle to other logic hardware to increase its reliability. Irving S. Reed, Albert C. L. Chiang |
IEEE Trans. Computers | 2 |
| 1970 | Arithmetic norms and bounds of the arithmetic AN codesabstractProperties of integers, related to the generation of the arithmetic AN codes, are investigated in this paper. A programmable algorithm for the computation of the binary norm of an arbitrary integer is developed. A table of norms of the natural numbers is generated and from this the distribution of integers of a given norm is found. These results are used to compute bounds on the size of ane-fold or less error-correcting AN code and to derive some further properties of single- and double-error-correcting AN codes. Albert C. L. Chiang, Irving S. Reed |
IEEE Trans. Inf. Theory | 1 |