We recognize that the execution of many dynamic instructions has no consequence on the overall execution of a program. For example, the execution of a correctly predicted conditional branch instruction, as well as all the instructions leading up to it, is inconsequential. We propose a clustered architecture that steers consequential instructions to the primary cluster and inconsequential ones to the secondary cluster called the I-Pipe, which is less capable and thereby more area and power efficient. The proposed architecture also entails minimal inter-cluster communication, thereby greatly reducing the complexities of inter-cluster result buses. Such a steering policy helps increase the performance as the consequential instructions do not face any interference from the inconsequential ones. We demonstrate a 42% area reduction as compared to a baseline single cluster (Tigerlake-based) architecture, a 18.5% power reduction in the SPEC CPU2017 suite (13.7% power reduction in GAPBS), and a 5.15% performance uplift in the SPEC CPU2017 suite (10.22% in the GAPBS suite).

In post-silicon validation, the first step when an erroneous behavior is uncovered by a long-running test case is to reproduce the observed behavior in a shorter execution. This makes it amenable to use a variety of tools and techniques to debug the error. In this work, we propose a tool called Gru, that takes a long execution trace as input and generates a set of executables, one for each section of the trace. Each generated executable is guaranteed to faithfully replicate the behavior observed in the corresponding section of the original, complex test case independently. This enables the generated executables to be run simultaneously across different silicon samples, thereby allowing further debugging activities to proceed in parallel. The generation of executables does not require the source code of the complex test case and hence supports privacy-aware debugging in scenarios involving sensitive Intellectual Properties (IPs). We demonstrate the effectiveness of this tool on a collection of 10 EEMBC benchmarks that are executed on a bare-metal LEON3 SoC.

Systems-on-chip (SoCs) are increasingly being composed of designs provided by different organizations. When such an SoC miscomputes or performs below expectation in-field, it is unclear which of the on-chip components caused the failure. The customer would like to use SoCs that provide the property of accountability, wherein the failure-causing component, and consequently its designing organization, can be unambiguously detected. Since it is a matter of trust, the various parties involved desire formal guarantees regarding any accountability solution. The solution must find the guilty component(s) in the event of a chip failure. Additionally, the solution must not falsely implicate any component that functioned correctly. This article formally describes the property of accountability, a formal methodology of constructing an accountability solution, and a formal game-theory based methodology to reason about and prove the viability of a proposed solution. We explore the entire space of solutions, and characterize the attack surface and methods to provide accountability for each setting. We show non-intuitive results in this article where seemingly simple solutions actually provide very powerful theoretical guarantees in terms of accountability.

When modern systems-on-chip (SoCs), containing designs from different organizations, miscompute or underperform in the field, discerning the responsible component is a non-trivial task. A perfectly accountable system is one in which the on-chip component at fault is always unambiguously detected. The achievement of accountability can be greatly aided by the collection of runtime information that captures the events in the system that led to the error. Such information collection must be fair and impartial to all parties. In this article, we prove that logging messages communicated between components from different organizations is sufficient to provide accountability, provided the logs are authentic. We then construct a solution based on this premise, with an on-chip trusted auditing system to authenticate the logs. We present a thorough design of the auditing system, and demonstrate that its performance overhead is a mere 0.49%, and its area overhead is a mere 0.194% (in a heterogeneous 48 core, 400 mm 2 chip). We also demonstrate the viability of this solution using three representative bugs found in popular commercial SoCs.

Lock-based parallel programs are easy to write. However, they are inherently slow as the synchronization is blocking in nature. Non-blocking lock-free programs, which use atomic instructions such as compare-and-set (CAS), are significantly faster. However, lock-free programs are notoriously difficult to design and debug. This can be greatly eased if the primitives work on multiple memory locations instead of one. We propose MCAS, a hardware implementation of a multi-word compare-and-set primitive. Ease of programming aside, MCAS-based programs are 13.8X and 4X faster on an average than lock-based and traditional lock-free programs respectively. The area overhead, in a 32-core 400mm2 chip, is a mere 0.046%.

Soft errors have become a serious cause of concern with reducing feature sizes. The ability to accommodate complex, Simultaneous Multithreading (SMT) cores on a single chip presents a unique opportunity to achieve reliable execution, safe from soft errors, with low performance penalties. In this context, we present FluidCheck , a checker architecture that allows highly flexible assignment and migration of checking duties across cores. In this article, we present a mechanism to dynamically use the resources of SMT cores for checking the results of other threads, and propose a variety of heuristics for migration of such checker threads across cores. Secondly, to make the process of checking more efficient, we propose a set of architectural enhancements that reduce power consumption, decrease the length of the critical path, and reduce the load on the Network-on-Chip (NoC). Based on our observations, we design a 16 core system for running SPEC2006 based bag-of-tasks applications. Our experiments demonstrate that fully reliable execution can be attained with a mere 27% slowdown, surpassing traditional redundant threading based techniques by roughly 42%.

ABSTRACT We study the problem of intruder tracking with non‐stealthy sensors, i.e., sensors whose ON/OFF state can be detected by an intruder, sometimes in advance. The sensor field is assumed to be operating with a sleep schedule to conserve energy. Both motion sensors and presence sensors are considered. We provide a rigorous basis for the study of this scenario by defining a new intruder model, the Ideal Intruder, that knows the entire sleep schedule of all the sensors in the field. More realistic intruders that have spatially and temporally limited knowledge of the sensor states are also defined. We study the well‐known Random Independent Sleep (RIS) scheduling scheme with a single parameterp, giving mathematical bounds for the ideal intruder's crossing time in the motion sensor case and showing that the crossing probability in the presence sensor case undergoes a sharp transition aspincreases. Further, we show that non‐ideal intruders perform almost as well as the ideal intruder against RIS. Motivated by this finding and by the comparison between Barrier Coverage and RIS, we define a new sleep scheduling scheme, Spotlight, that is more robust to faults than Barrier Coverage and more effective than RIS. But more than that, Spotlight is shown to be specifically suited to the non‐stealthy case because a non‐ideal intruder, that is, one with limited information performs significantly worse against it than the ideal intruder. Spotlight, therefore, apart from being a novel and interesting sleep scheduling scheme in its own right, also illustrates the power of the analytical framework we introduce in this paper. Copyright © 2013 John Wiley & Sons, Ltd.