In recent years, spiking neural networks (SNNs) have progressively closed the performance gap with convolutional neural networks (CNNs), which are renowned for their success in complex artificial intelligence tasks. However, most existing SNN accelerators suffer from limited flexibility, lacking support for diverse convolutional topologies and struggling to deploy complex SNN models. To address these challenges, this article proposes a reconfigurable neuromorphic architecture, SConvNSys, tailored for accelerating spiking CNNs (SCNNs) across a wide range of applications. A fast, sparse detection technique, coupled with a dedicated sparse response unit, is introduced to effectively exploit the spatio-temporal sparsity inherent in spike-based computation. On this basis, a reconfigurable spiking convolution dataflow is designed to optimize computation across various SCNN structures. The proposed architecture supports multiple convolution types, including standard, transposed, dilated, and residual convolutions. Implemented on a field-programmable gate array (FPGA), SConvNSys achieves competitive results: for image classification, it attains recognition accuracies of 91.48% on CIFAR-10 and 68.54% on CIFAR-100, with a power consumption of just 1.8 W and a processing rate of 73 frames/s. In image segmentation tasks, it reaches 99.00% segmentation accuracy at 153 frames/s. For object detection, the proposed detection model achieves a mean intersection over union (MIoU) of 74.20%, with 0.11 giga operations (GOP) of convolutional computation, resulting in a throughput of 27.4 giga operations per second (GOPS) and an energy efficiency of 15.23 GOPS/W.

ABSTRACT Electroencephalography (EEG) is a crucial tool for diagnosing neurological disorders like epilepsy. While Artificial Neural Networks (ANNs) have shown strong performance, their large parameter counts and high power consumption limit their practical application. Spiking Neural Networks (SNNs), with their inherent sparsity and parallelism, offer a promising solution; yet most existing SNN models for epilepsy detection are confined to binary classification and fail to fully exploit the rich spatiotemporal dependencies within EEG data. To address these limitations, this study proposes a lightweight Bidirectional Spiking Recurrent Neural Network (Bi‐SRNN) for advanced seizure stage classification. We employ Step‐Forward (SF) encoding to mitigate information loss from high‐frequency EEG oscillations and introduce the Bi‐SRNN architecture, based on the Adaptive Leaky Integrate‐and‐Fire (ALIF) model, to specifically enhance multi‐class classification performance and capture long‐term temporal features. Our model achieved accuracies of 100% and 99.00% in binary and ternary classification tasks on the public Bonn dataset through five‐fold cross‐validation, also achieving strong results on the New Delhi dataset. Furthermore, in transfer learning experiments where the model pre‐trained on the Bonn dataset was applied to new datasets, it demonstrated good generalization performance, also achieving strong results on the New Delhi dataset. With superior performance in both accuracy and model efficiency, the proposed method is well‐suited for deployment on edge devices, offering a more effective tool to assist in clinical diagnosis and treatment.

Neural style transfer is a prominent AI technique for creating captivating visual effects and enhancing user experiences . However, most current methods inadequately handle panoramic images, leading to a loss of original visual semantics and emotions due to insufficient structural feature consideration. To address this, a novel panorama arbitrary style transfer method named PAST-Renderer is proposed by integrating deformable convolutions and distortion constraints . The proposed method can dynamically adjust the position of the convolutional kernels according to the geometric structure of the input image, thereby better adapting to the spatial distortions and deformations in panoramic images. Deformable convolutions enable adaptive transformations on a two-dimensional plane, enhancing content and style feature extraction and fusion in panoramic images. Distortion constraints adjust content and style losses, ensuring semantic consistency in salience, edge, and depth of field with the original image. Experimental results show significant improvements, with the PSNR (Peak Signal-to-Noise Ratio) and SSIM (Structural Similarity Index Measure) of stylized panoramic images’ semantic maps increasing by approximately 2–4 dB and 0.1–0.3, respectively. Our method PAST-Renderer performs better in both artistic and realistic style transfer, preserving semantic integrity with natural colors, realistic edge details, and rich thematic content.

Most of the existing methods for traffic sign recognition exploited deep learning technology such as convolutional neural networks (CNNs) to achieve a breakthrough in detection accuracy; however, due to the large number of CNN’s parameters, there are problems in practical applications such as high power consumption, large calculation, and slow speed. Compared with CNN, a spiking neural network (SNN) can effectively simulate the information processing mechanism of biological brain, with stronger parallel processing capability, better sparsity, and real-time performance. Thus, we design and realize a novel traffic sign recognition system [called SNN on FPGA-traffic sign recognition system (SFPGA-TSRS)] based on spiking CNN (SCNN) and FPGA platform. Specifically, to improve the recognition accuracy, a traffic sign recognition model spatial attention SCNN (SA-SCNN) is proposed by combining LIF/IF neurons based SCNN with SA mechanism; and to accelerate the model inference, a neuron module is implemented with high performance, and an input coding module is designed as the input layer of the recognition model. The experiments show that compared with existing systems, the proposed SFPGA-TSRS can efficiently support the deployment of SCNN models, with a higher recognition accuracy of 99.22%, a faster frame rate of 66.38 frames per second (FPS), and lower power consumption of 1.423 W on the GTSRB dataset.

Currently, the performance of spiking neural networks (SNNs) under complicated tasks is gradually close to that of convolutional neural networks (CNNs). However, the existing neuromorphic computing hardware architectures (NCHAs) for accelerating SNNs lack effective sparse detection and cannot realize effective spatio-temporal parallel computing, resulting in high inference latency. In this paper, we propose an improved neuromorphic computing hardware architecture (called SiBrain) with high accuracy, low power and low latency, consisting of a sparse spatio-temporal parallel processing element (S$^{2}$TP-PE) array for spike convolution and pooling computation and a fully-connected (FC) Core for spike FC computation. In the novel S$^{2}$TP-PE array, a S$^{2}$TP computation unit is designed by using time-step and channel parallel computation techniques to reduce the latency caused by multiple time-steps of SNN, and a sparse detection and response unit is presented based on channel-cache and block-multiplex to achieve the spike detection, response, and reuse. Combining the above kernel components, the SiBrain is built and implemented on Virtex-7 FPGA with 200MHz. The experimental results show that the SiBrain can effectively support the deployment of SCNN models with different sizes, and the deployed large-scale Spiking Visual-Geometry-Group (VGG) model can achieve the recognition accuracies of 90.25% and 66.97% on CIFAR-10 and CIFAR-100 with the power consumption of 1.5 W and the energy efficiency of 83 GSOPs/W. Compared with existing FPGA-based SNN accelerators, SiBrain has a maximum increase in inference speed of nearly 11 times and a maximum decrease in energy consumption of nearly 34 times, respectively.

Spiking neural network (SNN) has attracted extensive attention in large-scale image processing tasks. To obtain higher computing efficiency, the development of hardware architecture suitable for SNN computing has become a hot research topic. However, the existing hardware of spike neurons still has high computational complexity and they do not perform well enough on complicated datasets, and the neuromorphic system cannot support SNNs with different convolutional topologies, resulting in low efficiency of the system. To address the above problems, an optimized leaky integrated-and-fire (LIF) neuron called EPC-LIF and a neuromorphic hardware acceleration system (ELIF-NHAS) are designed and implemented based on the field-programmable gate array (Xilinx Kintex-7). First, the classical LIF neuron is designed using the optimization method of extended prediction correction (EPC), which can reduce the computation complexity and hardware resources with a maximum frequency of 439.95 MHz. The ELIF-NHAS is constructed and optimized with parallel and pipeline techniques for effectively running SNNs, working with a maximum frequency of 135.6 MHz. Then, the genetic algorithm is applied to adjust the membrane threshold of neurons for further improving the accuracy of SNNs. Furthermore, the ELIF-NHAS can support different SNNs with multilayer perceptron and convolutional neural network topologies (called SCNN), including traditional, depth-separate, and residual convolutions. The accuracy of multilayer SCNNs can achieve 99.10%, 90.29%, and 82.15% on MNIST, Fashion-MNIST, and SVHN datasets, respectively; and the speed and energy consumption achieve 1.21 ms/image and 1.19 mJ/image. Compared with existing systems, the ELIF-NHAS is more suitable for the deployment and inference of SNNs with higher speed and lower consumption.

Spiking neural network (SNN) can process discrete spikes and offers a high degree of real-time performance and excellent energy efficiency ratio. However, most current neuromorphic hardware platforms lack efficient driven algorithms and only support a single type of neuron model, which has slow speed and poor scalability. This paper proposes a general FPGA-based neuromorphic hardware acceleration platform (FPGA-NHAP), supporting the effective inference and acceleration of SNN network with low power, high speed and good scalability. First, a neuron computing unit is designed to simulate the both LIF and Izhikevich (IZH) neurons with the parallel spike caching and scheduling technique. Second, a novel integrated driven update algorithm is proposed to complete the spike encoding of external data, reducing the waiting time of neuron state update effectively. Third, the proposed platform is implemented using a RISC-V processor and a Xilinx FPGA, simulating 16,384 neurons and 16.8 million synapses with a power consumption of 0.535 W. Finally, two different three-layer SNN networks are deployed on the proposed platform for recognition tasks on the MNIST and Fashion-MNIST datasets, achieving the accuracy of 97.70%, 85.14% (LIF) and 97.81%, 83.16% (IZH), frame rates of 208 frame/s, 128 frame/s (LIF) and 206 frame/s, 141 frame/s (IZH), respectively.