We present a constraint-coding scheme to correct asymmetric magnitude-1 errors in multi-level non-volatile memories. For large numbers of such errors, the scheme is shown to deliver better correction capability compared with known alternatives, while admitting low-complexity of decoding. Our results include an algebraic formulation of the constraint, necessary and sufficient conditions for correctability, a maximum-likelihood decoder running in complexity linear in the alphabet size, and upper bounds on the probability of failing to correct t errors. Besides the superior rate-correction tradeoff, another advantage of this scheme over standard error-correcting codes is the flexibility to vary the code parameters without significant modifications.

We define multi-block interleaved codes as codes that allow reading information from either a small sub-block or from a larger full block. The former offers faster access, while the latter provides better reliability. We specify the correction capability of the sub-block code through its gap t from optimal minimum distance, and look to have full-block minimum distance that grows with the parameter t. We construct two families of such codes when the number of sub-blocks is 3. The codes match the distance properties of known integrated-interleaving codes, but with the added feature of mapping the same number of information symbols to each sub-block. As such, they are the first codes that provide read access in multiple size granularities and correction capabilities.

In recent years, due to the spread of multi-level nonvolatile memories (NVM), q-ary write-once memories (WOM) codes have been extensively studied. By using WOM codes, it is possible to rewrite NVMs t times before erasing the cells. The use of WOM codes enables to improve the performance of the storage device, however, it may also increase errors caused by inter-cell interference (ICI). This work presents WOM codes that restrict the imbalance between code symbols throughout the write sequence, hence decreasing ICI. We first specify the imbalance model as a bound d on the difference between codeword levels. Then a 2-cell code construction for general q and input size is proposed. An upper bound on the write count is also derived, showing the optimality of the proposed construction. The new codes are also shown to be competitive with known codes not adhering to the bounded imbalance constraint.

In recent years, due to the spread of multi-level nonvolatile memories (NVMs), q-ary write-once memory (WOM) codes have been extensively studied. By using WOM codes, it is possible to rewrite NVMs t times before erasing the cells. Use of WOM codes enables the improvement of the performance of the storage device; however, it may also increase errors caused by inter-cell interference (ICI). This paper presents WOM codes that restrict the imbalance between code symbols throughout the write sequence, hence decreasing ICI. We first specify the imbalance model as a bound d on the difference between codeword levels. Then, a two-cell code construction for general q and input size is proposed. An upper bound on the write count is also derived, showing the optimality of the proposed construction. In addition to direct WOM constructions, we derive closed form optimal write regions for codes constructed with continuous lattices. On the coding side, the proposed codes are shown to be competitive with known codes not adhering to the bounded imbalance constraint. On the memory side, we show how the codes can be deployed within flash wordlines, and quantify their bit-error rate advantage using accepted ICI models.

We present a constraint-coding scheme to correct large numbers of asymmetric magnitude-1 errors in multi-level non-volatile memories. The scheme is shown to deliver better correction capability compared to known alternatives, while admitting low-complexity of decoding. Our results include an algebraic formulation of the constraint, necessary and sufficient conditions for correctability, a maximum-likelihood decoder running in complexity linear in the alphabet size, and lower bounds on the probability to correct t errors. Besides the superior rate-correction tradeoff, another advantage of this scheme over standard error-correcting codes is the flexibility to vary the code parameters without significant modifications.

Multi-level memory cells are used in non-volatile memories to increase the storage density. Using multi-level cells, however, imposes lower read and write speeds, limiting their usability with high-performing applications. In this work we study the tradeoff between storage density and write/read speeds using codes. The contributions are codes that give high-performance write and read processes with minimal reduction in storage density. We describe the codes, give a detailed analytical treatment of their information rate and speed, provide encoding/decoding algorithms, and compare them with more basic access schemes and upper bounds. Using performance coding enables accessing the memory with variable access speeds, thus creating heterogenous storage devices serving a variety of applications with improved efficiency.

Multi-level memory cells are used in non-volatile memories in order to increase the storage density. Using multi-level cells, however, imposes higher read and write latencies limiting high speed applications. In this work we study the tradeoff between storage density and write/read performance using codes. The contributions are codes that give high-performance write and read processes with minimal reduction in storage density. We describe the codes, give an analytical treatment of their information rate and speed, and compare them with more basic access schemes and upper bounds.

For an array of memory cells that are read by threshold measurements, we ask the question of how to choose the measurements in the read sequence to minimize the number of measurements before the array is fully read. We propose and study analytically and experimentally various adaptive read algorithms, and provide corresponding lower bounds on the average number of measurements. We show that new two-dimensional read algorithms improve over the best one-dimensional ones. We further adapt the read algorithms to the case where the cell levels are not uniformly distributed, as motivated by partially-erased memory arrays.

For an array of memory cells that are read by threshold measurements, we ask the question of how to choose the measurements in the read sequence to minimize the number of measurements before the array is fully read. We propose and study analytically various adaptive read algorithms, and provide a corresponding lower bound on the average number of measurements. We show that new two-dimensional read algorithms improve over the best one-dimensional ones.