Synchronous clock distribution continues to be the dominant timing methodology for VLSI circuit designs. As processes shrink, clock speeds increase, and die sizes grow, an increasingly larger percentage of the clock period is being lost to skew and jitter budgets. Process, voltage, and temperature variations, especially those that are intra-die, increasingly upset the distribution of a synchronized clock signal, even in properly balanced clock tree networks. As a result, active clock deskewing systems are becoming necessary to tune out unwanted clock skew after chip fabrication. This paper first defines the operation of a specially designed phase detector, referred to as an up/down detector (UDD). Next, four of these UDDs are used as links to construct a stable, autonomously locking quadrantal ring tuning (QRT) configuration that effectively joins together four distributed delay-locked loops (DLLs) without the need for any system-level controller. This cyclic, self-controlled, quad-DLL ring tuning technique is then implemented hierarchically to dynamically adjust clock signal delays across an entire chip during normal circuit operation. A simplistic two-level QRT system is presented for a generic H-tree clock distribution network, demonstrating stable locking behavior and more than 50% average reduction in overall clock skew.

Frequency domain analysis of switched-capacitor and other clocked circuits including nonlinearities is a difficult problem requiring special attention. Conventional nonlinear frequency response methods are computationally intensive and time consuming for circuits with large transient components. In this paper, we present a novel technique for the rapid estimation of the nonlinear frequency response of switched-capacitor circuits. The analysis technique is formulated using a multifrequency sinusoidal excitation to drive the circuit into its steady-state condition. Then, the fundamental components are extracted using a frequency-directed Discrete Fourier Transform (DFT) in order to construct the frequency response. The key steps of this approach include the selection of noninterfering input frequencies and the determination of properly scaled input amplitudes. In addition, a method is proposed to reach steady-state quickly and to detect the steady-state condition for use in conjunction with the multifrequency approach described here.