Elevated on-chip temperatures significantly degrade performance, energy-efficiency, and lifetime of processors. The cooling system for a chip is typically designed to remove the worst-case heat generated per unit area. Cooling demand, however, spatially and temporally varies across a chip as hot spots occur on different locations with different intensities. Thus, designing a homogeneous cooling system for a chip can be inefficient. Recently, hybrid cooling strategies, such as integrating thermoelectric coolers (TECs) with microchannel liquid cooling, have been explored for hot spot mitigation. The efficiency of such a cooling system strongly depends on the operating point of each cooling method, as well as the locations and intensities of the hot spots. To this end, we first devise a compact thermal modeling method for the design and evaluation of hybrid cooling systems in a fast and accurate way. The proposed model provides up to four orders of magnitude speedup in simulation time compared to COMSOL multiphysics simulations with less than 2.9 °C average temperature error. Leveraging our fast model, we develop LoCool, a hybrid cooling optimization method, which jointly determines the most energy-efficient cooling settings for a given chip power distribution and temperature constraint. LoCool determines the liquid flow rate and the input current for each TEC depending on the cooling requirements for individual hot spots as well as for the background heat. Experimental evaluation shows up to 40% cooling energy savings compared to designing homogeneous cooling systems under the same thermal constraints.

Flexibility either in buffering or routing is a very promising solution for NoC congestion problem. In this paper, a new 3D router with flexible architecture is introduced and validated for 3D NoCs. In fact, the Flexible router architecture introduced in literature would be deadlock prone if it is incorporated in a 3D NoC domain. We successfully design the new buffering constraints and extensively evaluate its performance under various traffic scenarios using real benchmark applications. We show the great enhancement of the new candidate router architecture in comparison to the conventional 3D NoC router architecture. Finally, we show that this enhancement in performance comes at a very low impact in power and area; especially for large NoC sizes.

Three-dimensional (3D) integration using through-silicon vias (TSVs) offers advantages over traditional 2D integration, however there are still several challenges originated from stacking dies. The main challenges in 3D-ICs are the large area overhead of the TSVs, low yield due to stacking several dies, and the increased cost of fabrication. In this paper a TSV multiplexing technique using so called TSV-BOX is proposed, which substitutes two TSVs with one TSV plus some extra hardware, but totally resulting in smaller die area. However, it does not impact the performance of the circuit. The TSV-BOX increases the total yield and reduces power consumption and fabrication cost due to the reduced TSVs count. For a 100 mm2die with 2x 105TSV count and TSV diameter of 8 m, the TSV-BOX could achieve 10% reduction in area, a 78% reduction in cost, and finally the yield could be enhanced by 24 times the original yield.