This work presents an efficient hardware architecture for hyperspectral image rotation, based on a geometric matrix transformation combined with bilinear interpolation to enhance pixel accuracy. These operations are commonly used in hyperspectral image (HSI) registration processes to compensate for motion in the observed scene. The primary objective of this research is to minimize the computational resource usage of the algorithm while optimizing overall efficiency. To achieve this, a reconfigurable hardware architecture based on FPGA is employed, where the rotation algorithm is implemented as an accelerator using the Vitis HLS synthesis tool and the block flow mechanism. The FPGA-based solution with four cores achieved a latency of 0,445 ms and a throughput of 1396,9 MB/s, with an energy consumption of only 1,09 mJ. Additionally, an alternative implementation was carried out on a GPU-based architecture (Jetson Nano), resulting in a higher latency of 12,55 ms and an energy consumption of 62,75 mJ. The evaluation included energy consumption, comparison with other solutions reported in the literature, and quality metrics. The results demonstrate that the FPGA-based solution is more efficient in terms of resource utilization and energy consumption, with minimal error.

Abstract The automation of insect pest control activities implies the use of classifiers to monitor the temporal and spatial evolution of the population using computer vision algorithms. In this regard, the popularisation of supervised learning methods represents a breakthrough in this field. However, their claimed effectiveness is reduced regarding working in real-life conditions. In addition, the efficiency of the proposed models is usually measured in terms of their accuracy, without considering the actual context of the sensing platforms deployed at the edge, where image processing must occur. Hence, energy consumption is a key factor in embedded devices powered by renewable energy sources such as solar panels, particularly in energy harvesting platforms, which are increasingly popular in smart farming applications. In this work, we perform a two-fold performance analysis (accuracy and energy efficiency) of three commonly used methods in computer vision (e.g., HOG+SVM, LeNet-5 CNN, and PCA+Random Forest) for object classification, targeting the detection of the olive fly in chromatic traps. The training and testing of the models were carried out using pictures captured in various realistic conditions to obtain more reliable results. We conducted an exhaustive exploration of the solution space for each evaluated method, assessing the impact of the input dataset and configuration parameters on the learning process outcomes. To determine their suitability for deployment on edge embedded systems, we implemented a prototype on a Raspberry Pi 4 and measured the processing time, memory usage, and power consumption. The results show that the PCA-Random Forest method achieves the highest accuracy of 99%, with significantly lower processing time (approximately 6 and 48 times faster) and power consumption (approximately 10 and 44 times lower) compared with its competitors (LeNet-5-based CNN and HOG+SVM).

The proliferation of Internet of Things (IoT) technologies in various industrial sectors has brought forth new challenges that demand attention for achieving technological maturity. One such challenge is the lack of tools for emulating the diverse components present in IoT architectures, leading to the continuous verification of each component in the chain, which proves to be a complex task. This paper addresses the verification problem in Edge/Fog IoT platforms through comprehensive end-to-end testing. To tackle this challenge, we have developed a modular IoT simulator (SimIoT) capable of efficiently emulating thousands of IoT devices in realistic scenarios, including hospitals, airports, and smart cities. The simulator allows testing of Edge platforms without the need for programming expertise. Furthermore, we demonstrate the feasibility of our simulator by presenting a use case involving the profiling of an open-source IoT platform.

The general aim of a cognitive Cyber Physical System of Systems (CPSoS) is to provide managed access to data in a smart fashion such that sensing and actuation capabilities are connected. Whilst there is significant funding and research devoted to this area, focus remains purely on creating bespoke systems. This paper presents a novel approach, based on a set of components to leverage Situational Awareness and Smart Actuation in large manufacturing industries with the focus on enabling predictive maintenance for asset and abnormal situation management. This paper presents a novel generic platform, named AtiCoS, that combines case-based and common-sense reasoning, as the enabling methodologies for enhancing CPSoS with cognitive capabilities.

Remote sensing has gained relevance in the last years, mainly due to the emergence of UAVs carrying airborne imagery sensors. In this regard, the on-board data processing for on-the-fly making-decision applications is also gaining momentum. Nevertheless, these flight vehicles are still limited in terms of power budget and computational capacity, which hampers the handling of the hyperspectral data. Consequently, there is an emerging trend towards the development of more hardware-friendly algorithms suitable for an efficient implementation in parallel computing devices. In this sense, the LbL-FAD algorithm arose in response to the lack of causal anomaly detectors that could be easily integrated in push-broom-based acquisition systems. In this work, we have analysed the feasibility of the performance and power needs of the LbL-FAD algorithm in a mid-range re-configurable FPGA-SoC such as the XC7Z020 chip. Concretely, a highly optimized FPGA accelerator of the LbL-FAD method has been described for the line-by-line detection of anomalous spectra.

In this PhD dissertation, we propose a new testing approach for effectively managing hardware development risks, producing hardware designs with enough quality and reliability. Our proposal is based on the combination of high-level modelling and a unit testing framework in order to generate real hardware implementations for validating the designer intent, in order to keep a high cycle-accuracy and a low design effort. Such real hardware implementations are based on FPGAs, whose reconfigurability are key to provide a flexible verification environment, whereas unit testing frameworks have been extended to consider new testing requirements beyond pure functionality, such as timing analysis. Moreover, we provide a hardware library with two different types of components: 1) monitors to check internal variables at run time, keeping the errors to later trace them, and 2) double functions to reduce third-party dependencies.

Partial Reconfiguration is one of the most attractive features of FPGAs. This feature provides new computing possibilities, for instance we can change a part of the initial functionality after its deployment, where a complete configuration is not needed, and the total area required is reduced. However, the design of partially reconfigurable systems has been a complex task yet. This work try to facilitate the design process and proposes a new development flow, which reduces mistakes during first stages of the design and makes the building of partial reconfiguration projects easier. In addition, we provide a dedicated hardware component, which manages bit streams nd dynamic areas. This component speed up the reconfiguration time, accomplishing a speed about 180MB/s.