Anlin Liu

dblp:136/2795 · DBLP profile ↗
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5ranked-venue papers
1as first author
3since 2021 · last 2025
—ORCID · conflict

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 3 · 1 first-author · 3 since 2021Applied, interdisciplinary, general and emerging computing · 2Software engineering, systems software and programming languages · 1 · 1 since 2021
YearPublicationVenuePosition
2025 Comprehensive RISC- V Floating-Point Verification: Efficient Coverage Models and Constraint-Based Test Generation
abstract
The increasing complexity of processor architectures necessitates more rigorous functional verification. Floating-point operations, in particular, present significant challenges due to their extensive range of computational cases that require verification. This paper proposes a comprehensive approach for generating floating-point instruction sequences to enhance the verification of RISC-V. We introduce a constraint-based method for floating-point test generation and design efficient coverage models as input constraints for this process. The resulting representative floating-point tests are integrated with RISC-V instruction sequence generation through a memory-bound register update method. Experimental results demonstrate that our approach improves the functional coverage of RISC-V floating-point instruction sequences from 93.32% to 98.34%, while simultaneously reducing the number of required instructions by 66.67% compared to the Google RISCV-DV generator. Additionally, our method achieves more comprehensive coverage of floating-point types in instruction write-back data compared to RISCV-DV. Using the proposed approach, we successfully detect representative floating-point-related faults injected into the RISC-V processor CV32E40P, thereby demonstrating its effectiveness.
Tianyao Lu, Anlin Liu, Bingjie Xia, Peng Liu 0016
DATE2
2024 Enhancing Functional Verification with Dynamic Instruction Generation by Exploiting Processor Runtime States
abstract
As the architectural complexity of processors increases dramatically, rigorous functional verification remains essential to ensure performance and immunity from design bugs. A pivotal yet challenging aspect of functional verification is the generation of test instruction streams that are not only highly effective in coverage but also compact enough to significantly reduce verification time. In this paper, we introduce DIG, a novel Dynamic Instruction Generator that leverages processor runtime architectural states through an instruction set simulator. In essence, DIG accesses processor runtime information to produce instruction streams with valid semantics, effectively avoiding illegal memory accesses and infinite loops. The quality of these instruction streams is further enhanced by incorporating both intra-instruction and inter-instruction test knowledge. The effectiveness of DIG is demonstrated through a case study involving Western Digital’s open-source RISC-V core, VeeR EH2. Our experimental results indicate that DIG reduces the number of test instructions by as much as 62.50% and 86.11%, compared to the state-of-the-art random instruction generators, RISC-V DV and RISC-V Torture, respectively, while simultaneously achieving superior functional coverage.
Anlin Liu, Tianyao Lu, Yuhao Xi, Yangfan Liu, Peng Liu 0016
ITC1
2022 Terminator on SkyNet: a practical DVFS attack on DNN hardware IP for UAV object detection
abstract
With increasing computation of various applications, dynamic voltage and frequency scaling (DVFS) is gradually deployed on FPGAs. However, its reliability and security haven't been sufficiently evaluated. In this paper, we present a practical DVFS fault attack targeting at the SkyNet accelerator IP and successfully destroy the detection accuracy. With no knowledge about the internal accelerator structure, our attack can achieve more than 98% detection accuracy loss under ten vulnerable operating point pairs (OPPs). Meanwhile, we explore the local injection with 1 ms duration and next double the intensity which can achieve more than 50% and 74% average accuracy loss respectively.
Junge Xu, Bohan Xuan, Anlin Liu, Mo Sun 0001, Fan Zhang 0010, Zeke Wang, Kui Ren 0001
DAC3
2004 A study on thermal inertia approach for agricultural drought monitoring in Shaanxi Province, China by using NOAA/AVHRR data
abstract
Thermal inert in method is one of the main approaches for drought monitoring by using remotely sensed data. The method is widely used in the China North Plain which is relatively flat. In our study, we tried to apply the approach to the agricultural areas of Shaanxi Province in the Northwest China with terrain and climate varies. The results showed that apparent thermal inertia can be used to monitor the drought occurrence. Considering the effects of terrains, vegetation coverage and soil types, the more homogeneous the land surface is, the better correlation between the apparent thermal inertia mid surface soil moisture is
Xingmin Li, Anlin Liu, Shuyu Zhang 0001, Pengxin Wang
IGARSS2
2004 Soil thermal inertia estimation by combining afternoon and morning AVHRR data with a modified diurnal land surface temperature change model
abstract
A modified diurnal land surface temperature change model was developed for soil thermal inertia retrieval by using NOAA/AVHRR remotely sensed data. The modified thermal inertia model was used to estimate surface soil moisture contents in the Guanzhong Plain of Shaanxi Province in the Northwest China. The results showed that the retrieved values of soil thermal inertia converged when the Fourier series were set to 10 or greater than 10, and the values were in the range of ground measured values published in some related articles. For applications of the model, soil thermal inertia can be reversed by applying the second Fourier series approximation. Based on the significance and the range of the estimated surface soil moisture, we found the exponential model between soil thermal inertia and soil moisture had the best performance in estimating soil moisture contents
Pengxin Wang, Xingmin Li, Shuyu Zhang 0001, Anlin Liu
IGARSS6