As multi-core and Chiplet systems increase in complexity, the bottlenecks of traditional synchronous network-on-chip (NoC) in clocking, power, and timing closure have become a critical barrier to performance scaling. To address this challenge, asynchronous circuits offer a compelling path forward, yet existing designs often struggle with the tradeoff between performance, which typically relies on customization, and EDA flow compatibility, which is often compromised. This paper presents and implements a fully asynchronous, standard-cell-based NoC router paradigm, aimed at translating the theoretical advantages of asynchrony into a practical, industrially viable solution. The paradigm synergizes an innovative Mix-Rail encoding strategy with an EDA-flow-friendly Click-style asynchronous handshake circuit, ensuring full compatibility with mainstream commercial EDA toolchains. This methodology not only achieves high performance but also, through its inherent modularity and generality, facilitates straightforward integration with more advanced NoC technologies. We rigorously validated this design. A test chip fabricated and measured in a 22nm CMOS process achieves a state-of-the-art average latency of 0.63 ns and a high energy efficiency of 0.16 pJ/bit at 0.85V, outperforming published SOTA asynchronous baselines. Furthermore, system-level simulations confirm the performance superiority of the asynchronous approach against a functionally equivalent synchronous baseline. This work provides a robust solution for energy-efficient interconnects in next-generation heterogeneous computing systems.

High-speed optical transceivers are advancing towards lower noise and power consumption, necessitating enhanced transimpedance amplifier (TIA) designs. This paper presents a 25Gbps single-ended to differential (S2D) low-noise TIA implemented in 45nm SOI technology. The design utilizes AC-coupling capacitors and a cross-coupled capacitor pair to achieve differential output. To optimize noise and bandwidth performance, a high-gain, low-bandwidth input stage is followed by a continuous-time linear equalizer (CTLE). The CTLE incorporates inductive peaking and negative capacitance techniques, achieving a bandwidth extension ratio (BWER) of 3.9 with less than 0.5dB peaking. Post-simulation results demonstrate the TIA achieves a transimpedance gain of 57.1 dB and a bandwidth of 23.7 GHz, considering a photodiode capacitance of 70fF. The input average noise current spectral density is 10.9$pA/\sqrt{Hz}$, with a power consumption of 38mW at a 1.3V supply voltage.

This article presents a wide-band suppression technique of flicker phase noise (PN) by means of a gate–drain phase shift in a transformer-based complementary oscillator. We identify that after naturally canceling its second-harmonic voltage by the complementary operation itself, third-harmonic current entering the capacitive path is now the main cause of asymmetry in the rising and falling edges, leading to the$1/f$noise upconversion. A complete$1/f^{3}$PN analysis for the transformer-based complementary oscillator is discussed. By tuning gate–drain capacitance ratio, a specific phase-shiftrangeis introduced at the gate and drain nodes of the cross-coupled pair to mitigate the detrimental effects of ill-behaved third-harmonic voltage, thus lowering the flicker PN. To further reduce the area and improve the PN in the thermal region, we introduce a new triple-8-shaped transformer. Fabricated in 22-nm FDSOI, the prototype occupies a compact area of 0.01mm2and achieves$1/f^{3}$PN corner of 70kHz, PN of −110dBc/Hz at 1MHz offset, figure-of-merit (FoM) of −182dB at 9GHz, and 39% tuning range (TR). It results in the best FoM with normalized TR and area (FoMTA) of −214dB at 1MHz offset.

Mixed-Mode frequency-modulated continuous wave (FMCW) synthesizer has proved to achieve the widest bandwidth and longest period of FMCW only using a 26MHz reference. In this paper, we propose a frequency-model for it both in time-domain and s-domain. Time-domain model proves why this architecture is suitable for FMCW application and offers designers enough details about this architecture in systemlevel. And s-domain model allows an accurate quantitative analysis and estimation of FMCW frequency error. The difference between the frequency error estimation based on our model and the measured results is less than 6.7%.