This paper presents a high-efficiency dual-mode off-time controlled buck converter with a novel seamless and fast mode transition scheme. The proposed seamless fast mode transition (SFMT) technique employs a mode selector consisting of a voltage detector (VD) and ripple-to-digital conversion circuit (RDC), solving the prolonged frequency transition problem in conventional mode-switching methods. Additionally, the introduced dynamic sleep clock management adaptively disables idle circuits based on duty cycle variations, achieving high efficiency across wide load ranges. Implemented in 0.18-$\mu $m technology, the converter occupies$0.5525~mm^{2}$while operating from a 2.5-3.6 V input to deliver 1.2 V output. Measurement results demonstrate$93.7~\%$peak efficiency at 0.4 A load and$80.5~\%$high light-load efficiency at 1 mA. The design achieves$\mu $s slew rate) with 28-$\mu $s recovery time, while maintaining low output ripple. Compared with reported designs, the proposed buck converter achieves an outstanding figure-of-merit ($FoM_{1}$) of$7.26~\mu s/(A^{2}/mm^{2})$.

Compared with SiGe technology, the limits of low transition frequency and low transconductance per unit current of CMOS technology result in poor noise, narrow bandwidth, and high power consumption in high-speed transimpedance amplifiers. The aforementioned issues are further exacerbated while using a low-speed low-cost photodiode. In this study, an equalization technique is proposed to increase the feedback resistance$\boldsymbol {R_{F}}$, achieving low noise and bandwidth extension of the chip. A novel inductorless bandwidth extension technique is proposed to increase the bandwidth of high-speed channel by 37.5%. In addition, a new current reuse technique is proposed to inject the output stage’s tail current into the input stage to achieve a high gain, saving power consumption by 20%. We achieve 10-Gb/s operation with a 400-fF avalanche photodiode (APD) using 65-nm CMOS technology. The bandwidth is 6.8 GHz, the transimpedance gain is 66 dB$\boldsymbol{\Omega }$, the average input-referred noise current is 11.9 pA/$\surd $Hz, and the average sensitivity is −22.4 dBm at a BER of 1e−12. The SF-TIA chip takes up 0.56 mm2 and consumes 26 mA from a 3.3-V supply.

A Voltage Swing Self-Adjustable (VSSA) Match-Line (ML) Sensing Scheme is presented for Content-Addressable Memories (CAMs). A simple ML voltage detector instead of a complicated fully differential one is proposed which enables ML voltage swing approaching to zero. Meanwhile, the scheme improves the robustness against process variation by means of voltage swing self-adjustment. Post-layout simulation results show the proposed 64-word × 144-bit ternary CAM, using 55-nm 1.2-V standard CMOS process, achieves 0.18fJ/bit/search for the ML power dissipation with less than 750ps search time. Normalized ML Energy-Delay-Product (EDP) achieves 0.14 fJ·ns/bit/search which accounts for 53.8% and 16.1% that of [7] and [8] separately.

A 1.2-V piecewise curvature-corrected CMOS bandgap reference (BGR) is proposed. It features in utilizing piecewise nonlinear curvature-corrected current and rail-to-rail operational amplifier to a conventional first-order current-mode BGR. The corrected current is zero, exponential with temperature and proportional to the squared temperature in the lower, middle and higher temperature range (TR). The rail-to-rail operational amplifier biased by a current proportional to absolute temperature (PTAT) helps to provide negative feedback for the proposed BGR. Measured results indicate that the proposed BGR achieves temperature coefficient (TC) of 8.9 ppm/°C in the TR of -40°C-110°C without trimming, power supply rejection (PSR) of - 58 dB and line regulation of 2.4 mV/V in the supply range of 1.2-3.2 V. It is fabricated in CSMC 0.5-μ m mixed-signal CMOS process with power consumption of 48 μW and effective chip area of 0.1 mm2.

A 1-V piecewise curvature-corrected CMOS bandgap reference (BGR) is proposed. It features in utilizing piecewise corrected current to a conventional first-order current-mode BGR. The corrected current is zero, exponential with temperature and proportional to the squared temperature in the lower, middle and upper temperature range (TR). Simulated results indicate that proposed BGR achieves temperature coefficient (TC) of 1.18ppm/°C in the TR of -30-130°C, power supply rejection ratio (PSRR) of -52dB and line regulation of 0.1mV/V in the supply range of 1-1.8V. The maximum power consumption is 29.5¼W. It is designed in HJTC 0.18-¼m n-well CMOS process.