Demo Data from EDBT 2026 / reviewers in the wild / expert
Laertis Loutsis
dblp:136/8350
· DBLP profile ↗
1ranked-venue papers
0as first author
0since 2021 · last 2013
—ORCID · none
Domains — the database's venue-derived domains; a paper can count in several
Security and privacy · 1
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Network and information security
1 paper |
Systems and software security · 100% | |
| Computer architecture, parallel and distributed computing, and storage systems
1 paper |
Processor architecture and microarchitecture · 100% |
Topics — the 3 heaviest of 3, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Systems and software security › exploitation mitigation
code injection defense |
0.2 | 1 | 2013 | ASIST: architectural support for instruction set randomization · CCS 2013 |
Systems and software security › code randomization
instruction set randomization |
0.2 | 1 | 2013 | ASIST: architectural support for instruction set randomization · CCS 2013 |
Processor architecture and microarchitecture
hardware-assisted security |
0.2 | 1 | 2013 | ASIST: architectural support for instruction set randomization · CCS 2013 |
Methods — techniques the papers use, named apart from their topics
emulation · 0.3binary instrumentation · 0.3
| Year | Publication | Venue | Position |
|---|---|---|---|
| 2013 | ASIST: architectural support for instruction set randomizationabstractCode injection attacks continue to pose a threat to today's computing systems, as they exploit software vulnerabilities to inject and execute arbitrary, malicious code. Instruction Set Randomization (ISR) is able to protect a system against remote machine code injection attacks by randomizing the instruction set of each process. This way, the attacker will inject invalid code that will fail to execute on the randomized processor. However, all the existing implementations of ISR are based on emulators and binary instrumentation tools that (i) incur a significant runtime performance overhead, (ii) limit the ease of deployment of ISR, (iii) cannot protect the underlying operating system kernel, and (iv) are vulnerable to evasion attempts trying to bypass ISR protection. Antonis Papadogiannakis, Laertis Loutsis, Vassilis Papaefstathiou, Sotiris Ioannidis |
CCS | 2 |