Abstract As semiconductor manufacturing becomes increasingly outsourced to untrusted entities, Hardware Trojan (HT) attacks pose a critical threat to the security and reliability of modern integrated circuits. Machine learning models have improved the effectiveness of HT detection using Ring Oscillator Network (RON) side-channel data, yet recent work shows that these models are highly vulnerable to adversarial attacks. This paper evaluates the robustness of the Support Vector Machine (SVM) classifier, a leading algorithm in state-of-the-art HT detection frameworks, under gradient-based adversarial attacks. The proposed work demonstrates that high nominal accuracy does not ensure security against these attacks, which can reduce recall to zero. To strengthen resilience, three data-augmentation methods are investigated: SMOTE, Conditional Tabular Generative Adversarial Network (CTGAN), and Tabular Variational Autoencoder (TVAE). TVAE produces high-fidelity synthetic samples and substantially improves robustness, maintaining over 91% accuracy for nominal performance and over 88% accuracy under strong adversarial perturbations that cause a 100% attack success rate for the surrogate model. The results highlight the need to reframe hardware security evaluations beyond nominal accuracy toward adversarial robustness.

Discovering new vulnerabilities and implementing security and privacy measures are important to protect systems and data against physical attacks. One such vulnerability is impedance, an inherent property of a device that can be exploited to leak information through an unintended side-channel, thereby posing significant security and privacy risks. Unlike traditional vulnerabilities, impedance is often overlooked or narrowly explored, as it is typically treated as a fixed value at a specific frequency in research and design endeavors, leaving its potential for information leakage largely unexplored. This article demonstrates that the impedance of an embedded device is not constant and directly relates to the programs executed on the device. We define this phenomenon as impedance leakage and use this as a side-channel to extract software instructions from protected memory. Our experiment on the ATmega328P microcontroller and the Artix 7 FPGA indicates that the impedance side-channel can detect software instructions with 96.1% and 92.6% accuracy, respectively. Furthermore, we explore the dual nature of the impedance side-channel, highlighting the potential for beneficial purposes and the associated risk of intellectual property theft.

Hardware Trojans are deliberate malicious hardware modifications inserted in semiconductor Integrated Circuits (ICs) for the purpose of stealing or leaking sensitive information, as well as disrupting critical systems upon activation. Emerging hardware security research highlights the criticality of employing AI for effective detection within the semiconductor IC supply chain. The efficient detection of these malicious Trojan circuits is of utmost significance, as it holds paramount importance in cultivating trust within the semiconductor IC supply chain. However, prevailing detection methodologies, predominantly reliant on Side-Channel Analysis (SCA), often necessitate the utilization of golden chips for validation. This article heralds a new era in hardware Trojan detection, harnessing the prowess of unsupervised machine learning in conjunction with SCA to eliminate the need for golden data. Employing unsupervised clustering, the methodology not only showcased a superior false-positive rate but also demonstrated a comparable accuracy level when compared to supervised counterparts. Notably, the proposed model exhibited an impressive accuracy rate of 93%, particularly excelling in pinpointing diminutive Trojans triggered by concise events, surpassing the capabilities of preceding techniques. In conclusion, this research advances a paradigm in hardware Trojan detection, emphasizing its potential in enhancing the integrity of semiconductor IC supply chains.

This article introduces a novel, low-cost technique for hiding data in commercially available resistive-RAM (ReRAM) chips. The data is kept hidden in ReRAM cells by manipulating its analog physical properties through switching (set/reset) operations. This hidden data, later, is retrieved by sensing the changes in cells’ physical properties (i.e.,set/resettime of the memory cells). The proposed system-level hiding technique does not affect normal memory operations and does not require any hardware modifications. Furthermore, the proposed hiding approach is robust against temperature variations and the aging of the devices through normal read/write operation. The silicon results show that our proposed data hiding technique is acceptably fast with ~0.12bit/sof encoding and ~3.26Kbits/sof retrieval rates, and the hidden message is unrecoverable without the knowledge of the secret key, which is used to enhance the security of hidden information.

Many commercially available memory chips are fabricated worldwide in untrusted facilities. Therefore, a counterfeit memory chip can easily enter into the supply chain in different formats. Deploying these counterfeit memory chips into an electronic system can severely affect security and reliability domains because of their substandard quality, poor performance, and shorter lifespan. Therefore, a proper solution is required to identify counterfeit memory chips before deploying them in mission-, safety-, and security-critical systems. However, a single solution to prevent counterfeiting is challenging due to the diversity of counterfeit types, sources, and refinement techniques. Besides, the chips can pass initial testing and still fail while being used in the system. Furthermore, existing solutions focus on detecting a single counterfeit type (e.g., detecting recycled memory chips). This work proposes a framework that detects major counterfeit static random-access memory (SRAM) types by attesting/identifying the origin of the manufacturer. The proposed technique generates a single signature for a manufacturer and does not require any exhaustive registration/authentication process. We validate our proposed technique using 345 SRAM chips produced by major manufacturers. The silicon results show that the test scores (F1score) of our proposed technique of identifying memory manufacturer and part-number are 93% and 71%, respectively.

Approximate computing (AC) leverages the inherent error resilience and is used in many big-data applications from various domains such as multimedia, computer vision, signal processing, and machine learning to improve systems performance and power consumption. Like many other approximate circuits and algorithms, the memory subsystem can also be used to enhance performance and save power significantly. This paper proposes an efficient and effective systematic methodology to construct an approximate non-volatile magneto-resistive RAM (MRAM) framework using consumer-off-the-shelf (COTS) MRAM chips. In the proposed scheme, an extensive experimental characterization of memory errors is performed by manipulating the write latency of MRAM chips which exploits the inherent (intrinsic/extrinsic process variation) stochastic switching behavior of magnetic tunnel junctions (MTJs). The experimental results, involving error-resilient image compression and machine learning applications, reveal that the proposed AC framework provides a significant performance improvement and demonstrates a reduction in MRAM write energy of ~47.5% on average with negligible or no loss in output quality.

Electronic counterfeiting is a longstanding problem with adverse long-term effects for many sectors, remaining on the rise. This article presents a novel low-cost technique to embed watermarking in devices with resistive-RAM (ReRAM) by manipulating its analog physical characteristics through switching (set/reset) operation to prevent counterfeiting. We develop a system-level framework to control memory cells' physical properties for imprinting irreversible watermarks into commercial ReRAMs that will be retrieved by sensing the changes in cells' physical properties. Experimental results show that our proposed ReRAM watermarking is robust against temperature variation and acceptably fast with ~0.6bit/min of imprinting and ~15.625bits/s of retrieval rates.

Memory-based physical unclonable functions (mPUFs) are widely accepted as highly secure because of the unclonable and immutable nature of manufacturer process variations. Although numerous successful attacks have been proposed against PUFs, mPUFs are resistant to non-invasive attacks as the mPUF does not support the open-access protocol. Hence, existing attacks against mPUFs mostly rely on invasive/semi-invasive techniques or at least require physical access to the target device, which is not always feasible. In this paper, we experimentally demonstrate that signatures generated from two memory chips may have highly correlated properties if they possess the same set of specifications and a similar manufacturing facility, which is used to mount a non-invasive attack against memory-based PUFs. Our proposed technique shows that if an attacker has access to a device similar to the victim's one, the attacker might be able to guess up to ~45% of the challenge-response pairs of a 64-bit SRAM PUF.

True random number generation (TRNG) plays an important role in security applications and protocols. In this article, we propose an effective technique to generate a robust true random number using emerging, energy-efficient, nonvolatile, consumer-off-the-shelf (COTS) ferroelectric random access memory (FRAM) chips. In the proposed method, we extract inherent randomness from internal ferroelectric capacitors by exploiting latency variation across cells within FRAM. Hardware results and subsequent National Institute of Standards and Technology (NIST) statistical test suite (STS) testing indicate that the proposed latency-based TRNG is robust over a wide range of operating conditions at speeds of 6.23 Mb/s using COTS, silicon FRAM chips from Cypress Semiconductor Corporation.

With the rapid growth of the electronics market, counterfeiting of integrated circuits (ICs), in particular IC recycling, has become a serious issue in recent years. Recycled ICs are those harvested from old systems and resold in the supply chain as new. Such ICs exhibit lower performance and shorter lifetime and, as a result, pose threats to the security and reliability of electronic systems. In this paper, we propose a recycled IC detection framework called static random-access memory (SRAM)-based countermeasure against IC recycling (SCARe) to detect the aging of SRAM cells. Our framework can be applied to both standalone SRAM chips and system on chips with embedded SRAM. For each SRAM under detection, statistical analysis is conducted to differentiate the recycled and new ICs. To mimic the practical aging scenario, 16 commodity SRAM chips from three different manufacturers and different technology nodes (e.g., 90, 110, and 130 nm) are stressed under high-temperature and supply-voltage conditions for different periods of time. The experimental results from new and aged SRAM chips, which represents recycled ICs, demonstrate that our proposed technology can achieve extremely high-detection success rate (no lower than 96.5%). The minimal in-field usage, which can be detected by SCARe, is 7 h.

Physically Unclonable Functions (PUFs) have emerged as a promising security primitive for low-cost authentication and cryptographic key generation. However, PUF stability with respect to temporal variations still limits its utility and widespread acceptance. Previous techniques in the literature have focused on improving PUF robustness against voltage and temperature variations, but the issues associated with aging have been largely neglected. In this paper, we propose a reliable pair selection algorithm (RePa) that can generate reliable keys from an RO-PUF under aging, voltage, and temperature variations. The RePa approach selects RO pairs with both initial frequency difference and aging rate/slope in mind. The aging slope is predicted by exploiting correlation that exists between frequency variation with respect to voltage and frequency variation with respect to aging. We evaluate RePa with simulations to show that it achieves significant improvement over the current state of the art in terms of reliability and cost. The proposed approach can achieve ~ 3.0x more robust key with only ~ 2.3x more ROs required than the conventional RO-PUF pair selection for the same key size.

A Physically Unclonable Function (PUF) is a structure that when issued a challenge, it produces a unique and reliable response which can be used as an identifier or a cryptographic key. SRAM PUFs create unique responses upon power up as certain SRAM cells output a '1' or '0' with high probability due to uncontrollable process variations. A current challenge in SRAM PUFs is their sensitivity to temperature and voltage variations as well as aging. By creating algorithms that isolate stable bits quickly and with minimal testing, the use of SRAM PUF should become more practical. In this paper, we explore the selection of stable bits through enrollment under different conditions (temperature, voltage, and aging) and also by exploiting previously undiscovered interactions between neighboring SRAM cells. We develop metrics that analyze the impact of each neighboring cell and each enrollment condition. Our metrics can be used to identify the best cells and conditions for stable bit selection. We have analyzed data from Spartan 3 FPGA and our metrics identify the best neighborhood size (16 stable neighbors) and best enrollment condition pair (high temperature, high voltage and low temperature).

True random number generators (TRNGs) are needed for a variety of security applications and protocols. The quality (randomness) of TRNGs depends on sensitivity to random noise, environmental conditions, and aging. Random sources of noise improve TRNG quality. In older or more mature technologies, the random sources are limited resulting in low TRNG quality. Prior work has also shown that attackers can manipulate voltage supply and temperature to bias the TRNG output. In this paper, we propose bias detection mechanisms and a technology independent TRNG (TI-TRNG) architecture. The TI-TRNG enhances power supply noise for older technologies and uses a self-calibration mechanism that reduces bias in TRNG output due to aging and attacks. Experiment results on 130nm, 90nm, and 45nm FPGAs demonstrate the quality of random sequences from the TI-TRNG across aging and different environmental conditions.

Physically Unclonable Functions (PUFs) have emerged as a security block with the potential to generate chip-specific identifiers and cryptographic keys. However it has been shown that the stability of these identifiers and keys is heavily impacted by aging and environmental variations. Previous techniques have mostly focused on improving PUF robustness against supply noise and temperature but aging has been largely neglected. In this paper, we propose a new aging resistant design for the popular ring-oscillator (RO)-PUF. Simulation results demonstrate that our aging resistant RO-PUF (called ARO-PUF) can produce unique, random, and more reliable keys. Only 7.7% bits get flipped on average over 10 years operation period for an ARO-PUF due to aging where the value is 32% for a conventional RO-PUF. The ARO-PUF shows an average interchip HD of 49.67% (close to ideal value 50%) and better than the conventional RO-PUF (~45%). With lower error, ARO-PUF offers ~ 24X area reduction for a 128-bit key because of reduced ECC complexity and smaller PUF footprint.

Auto-focusing is a key feature of modern camera systems that ensures a focused image is captured without the need for any user intervention. Passive auto-focusing is achieved based on a measure of sharpness or a sharpness function that is extracted from a series of images at different focal positions. With the rapid growth of stereo camera systems for 3D applications, this paper introduces a sharpness function when a series of stereo image pairs are captured at different focal positions. This function is defined based on the joint information between the left and right images. A comparison is carried out between the introduced sharpness function and the conventional sharpness functions when considering the left and right images separately in terms of sharpness accuracy and computation time.

Although many face detection algorithms have been introduced in the literature, only a handful of them can meet the real-time constraints of mobile devices. This paper presents the real-time implementation of our previously introduced face detection algorithm on a mobile device. The steps taken to achieve such a real-time implementation are discussed. Real-time comparison results with the widely used Viola-Jones face detection algorithm in terms of detection rate and processing speed are presented to demonstrate the robustness of our real-time solution.

Although there are many face detection algorithms in the literature, only a handful of them meet the real-time constraints of a software-based solution without using any dedicated hardware engine. This paper presents a real-time and robust solution for mobile platforms which in general have limited computation and memory resources as compared to PC platforms. This solution involves combining our two previous real-time implementations for mobile platforms to address the shortcoming of each implementation. The first implementation provides an online or on-the-fly light source calibration for the second implementation which is found to be robust to various face poses or orientations. The real-time results obtained on an actual mobile platform indicate both the real-time and robustness capabilities of this hybrid face detection solution.

Signals and systems lab courses that are currently offered at many universities are mostly based on text-based programming languages and environments, in particular MATLAB. This paper presents an alternative programming approach in these courses by combining textual with graphical programming. This hybrid programming approach offers code interactivity in a time-efficient manner. Example labs are presented to demonstrate how this approach allows students to interact and experiment with their codes to gain a better understanding of the signal processing concepts.