Two-dimensional time-division-multiplexing (2DTDM) was recently proposed to minimize both the time for testing 3D Systems-on-Chips (SoCs) and the number of through-silicon-vias (TSVs). Even though 2D-TDM exploits the short vertical interconnections to transfer very fast the test-data to the various layers of the stack, the bus-based test-access-mechanism (TAM) at each layer imposes excessive routing overhead and long intra-die delays that compromise the test-time benefits, especially when the stack layers are unbalanced in terms of test-times. In this paper, we propose a new TDM-based TAM architecture for 3D SoCs, which supports non-regular division of the frequency among the various layers of the stack using very short daisy-chain intra-die connections. The proposed 3D TAM architecture is optimized by the means of the K3 design-automation process that combines the Kruskal algorithm, the Complete Karmarkar-Karp heuristic and a new optimization heuristic proposed in this paper. Experiments performed on a 3D benchmark integrated circuit (IC) show that significant test-time and routing savings are achieved.

Software-based self-test (SBST) is being widely used in both manufacturing and in-the-field testing of processor-based devices and Systems-on-Chips. Unfortunately, the stuck-at fault model is increasingly inadequate to match the new and different types of defects in the most recent semiconductor technologies, while the explicit and separate targeting of every fault model in SBST is cumbersome due to the high complexity of the test-generation process, the lack of automation tools, and the high CPU-intensity of the fault-simulation process. Moreover, defects in advanced semiconductor technologies are not always covered by the most commonly used fault-models, and the probability of defect-escapes increases even more. To overcome these shortcomings we propose the first fault-independent SBST method. The proposed method is almost fully automated, it offers high coverage of non-modeled faults by means of a novel SBST-oriented probabilistic metric, and it is very fast as it omits the time-consuming test-generation/fault-simulation processes. Extensive experiments on the OpenRISC OR1200 processor show the advantages of the proposed method.

Through-silicon vias (TSVs) are used as high-speed vertical interconnects between dies in a 3-D system-on-a-chip (SoC). However, their speed cannot be exploited during test application due to inherent limitations of the scan-chains of the cores, which prevent the use of high shift frequencies during the scan-in/out operations. Moreover, due to their high area cost, only a limited number of TSVs can be utilized for test application. As a result, TSVs become the bottleneck for transferring the large volume of test-data to the various layers of the stack, and the time for testing the 3-D chip increases a lot. In this paper, we propose an efficient test-access mechanism (TAM) architecture that exploits the high speed of TSVs to minimize the time for testing 3-D SoCs. The proposed TAM architecture is based on a 2-D time-division-multiplexing approach, and by the means of a very effective test-scheduling method, it offers significant savings in test-time, TSV-count and TAM-cost under power and thermal constraints. Extensive experiments on two 3-D benchmark SoCs show the benefits of the proposed method.

The use of multiple voltage levels introduces new challenges for testing multi-Vddsystems-on-chip (SoCs). Timedivision-multiplexing (TDM) tackles many of these challenges and offers very effective test-schedules. However, the effectiveness of TDM for minimizing test time depends on the test-access-mechanism (TAM) in the SoC. Single-VddTAM optimization techniques consider neither the highly constrained test environment of multi-VddSoCs nor the benefits provided by TDM, therefore they are not suitable for multi-VddSoCs. In this paper, we propose the first TAM optimization technique for multi-VddSoCs. The proposed method exploits unique scheduling opportunities and flexibility offered by TDM, and by the means of a branch-&-bound approach, it quickly identifies the most effective TAM configurations. Experiments using large benchmark SoCs as well as SoCs from industry highlight the benefits of the proposed technique on multi-Vdddesigns, for both single-site and multisite test applications.

Through-silicon vias (TSVs) are used as high-speed interconnects between dies in a 3D System-on-Chip (SoC). However, their speed cannot be utilized during test application due to inherent limitations of the scan chains of the cores, which prevent the use of high shift frequencies. Moreover, due to their high area cost, only a limited number of TSVs can be used for test application. As a result, the time needed for transferring test data to the cores in multiple dies can be considerable. We propose an efficient test-access mechanism (TAM) architecture, which exploits the high speed of TSVs to minimize the time for testing 3D SoCs. By the means of time-division multiplexing and an effective test scheduling method, the proposed TAM architecture offers significant savings in test time, TSV count and TAM cost.

The use of multiple voltage levels introduces new challenges for testing Multi-VddSoCs. Time-Division-Multiplexing (TDM) tackles many of these challenges and offers very effective test-schedules. However, the effectiveness of TDM for minimizing test time depends on the Test-Access-Mechanism (TAM) in the SoC. Single-VddTAM optimization techniques consider neither the highly constrained test environment of multi-VddSoCs nor the benefits provided by TDM, therefore they are not suitable for multi-VddSoCs. In this paper, we propose the first TAM optimization technique for multi-VddSoCs. The proposed method exploits unique scheduling opportunities and flexibility offered by TDM, and by the means of a Branch-&-Bound approach, it quickly identifies the most effective TAM configurations. Experiments using SoCs from industry highlight the benefits of the proposed technique on multi-Vdddesigns, for both single-site and multi-site test applications.